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Fixes for in-tree barstools

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This commit is contained in:
Jerry Zhao
2024-04-19 11:30:15 -07:00
parent d7060f4b5a
commit 9436aea1e8
26 changed files with 40 additions and 43 deletions
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2
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleI
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import barstools.iocell.chisel._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))

2
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -7,7 +7,7 @@ import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import barstools.iocell.chisel._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector

2
generators/chipyard/src/main/scala/example/CustomChipTop.scala
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@@ -6,7 +6,7 @@ import chipyard.iobinders._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy.{InModuleBody}
import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
import barstools.iocell.chisel._
import chipyard.iocell._
import chipyard._
import chipyard.harness.{BuildTop}
import sifive.blocks.devices.uart._

2
generators/chipyard/src/main/scala/example/FlatChipTop.scala
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@@ -13,7 +13,7 @@ import chipyard.{BuildSystem, DigitalTop}
import chipyard.harness.{BuildTop}
import chipyard.clocking._
import chipyard.iobinders._
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.serdes.{SerialTLKey}
class WithFlatChipTop extends Config((site, here, up) => {

2
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.devices.debug.{SimJTAG}
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.dram.{SimDRAM}
import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
import testchipip.soc.{TestchipSimDTM}

2
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
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@@ -27,7 +27,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}

4
generators/chipyard/src/main/scala/iocell/Analog.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details
package barstools.iocell.chisel
package chipyard.iocell
import chisel3._
import chisel3.util.{HasBlackBoxResource}
@@ -10,7 +10,7 @@ class AnalogConst(value: Int, width: Int = 1)
extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width)))
with HasBlackBoxResource {
val io = IO(new Bundle { val io = Analog(width.W) })
addResource("/barstools/iocell/vsrc/Analog.v")
addResource("/vsrc/Analog.v")
}
object AnalogConst {

2
generators/chipyard/src/main/scala/iocell/IOCell.scala
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@@ -1,6 +1,6 @@
// See LICENSE for license details
package barstools.iocell.chisel
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}

2
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -26,7 +26,7 @@ import firesim.configs.MemModelKey
import tracegen.{TraceGenSystemModuleImp}
import cva6.CVA6Tile
import barstools.iocell.chisel._
import chipyard.iocell._
import chipyard.iobinders._
import chipyard._
import chipyard.harness._