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Fix corner case in compiling a small mem using a large lib (#32)

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* Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
This commit is contained in:
edwardcwang
2018-04-26 10:33:55 -07:00
committed by GitHub
parent f7634b82cd
commit 93bf7895be
3 changed files with 155 additions and 67 deletions
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34
macros/src/test/scala/SpecificExamples.scala
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@@ -1,3 +1,4 @@
// See LICENSE for license details.
package barstools.macros
import mdf.macrolib._
@@ -1232,6 +1233,39 @@ circuit smem_0_ext :
compileExecuteAndTest(mem, lib, v, output)
}
class SmallTagArrayTest extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleTestGenerator {
// Test that mapping a smaller memory using a larger lib can still work.
override def memWidth: Int = 26
override def memDepth: Int = 2
override def memMaskGran: Option[Int] = Some(26)
override def memPortPrefix: String = ""
override def libWidth: Int = 32
override def libDepth: Int = 64
override def libMaskGran: Option[Int] = Some(1)
override def libPortPrefix: String = ""
override def extraPorts: Seq[MacroExtraPort] = Seq(
MacroExtraPort(name = "must_be_one", portType = Constant, width = 1, value = 1)
)
override def generateBody(): String =
s"""
| inst mem_0_0 of $lib_name
| mem_0_0.must_be_one <= UInt<1>("h1")
| mem_0_0.clk <= clk
| mem_0_0.addr <= addr
| node dout_0_0 = bits(mem_0_0.dout, 25, 0)
| mem_0_0.din <= bits(din, 25, 0)
| mem_0_0.mask <= cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), bits(mask, 0, 0))))))))))))))))))))))))))))))))
| mem_0_0.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1"))
| node dout_0 = dout_0_0
| dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0"))
""".stripMargin
compileExecuteAndTest(mem, lib, v, output)
}
class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
val mem = s"mem-RocketChipTest.json"
val lib = s"lib-RocketChipTest.json"