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This commit is contained in:
Edward Wang
2017-07-31 15:36:43 -07:00
committed by edwardcwang
parent 3730f76fa3
commit 93331cd26d
1 changed files with 26 additions and 19 deletions
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45
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -53,11 +53,14 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
} }
// Convenience function for running both compile, execute, and test at once. // Convenience function for running both compile, execute, and test at once.
def compileExecuteAndTest(mem: String, lib: String, v: String, output: String, synflops: Boolean = false): Unit = { def compileExecuteAndTest(mem: String, lib: Option[String], v: String, output: String, synflops: Boolean): Unit = {
compile(mem, lib, v, synflops) compile(mem, lib, v, synflops)
val result = execute(mem, lib, synflops) val result = execute(mem, lib, synflops)
test(result, output) test(result, output)
} }
def compileExecuteAndTest(mem: String, lib: String, v: String, output: String, synflops: Boolean = false): Unit = {
compileExecuteAndTest(mem, Some(lib), v, output, synflops)
}
// Compare FIRRTL outputs after reparsing output with ScalaTest ("should be"). // Compare FIRRTL outputs after reparsing output with ScalaTest ("should be").
def test(result: Circuit, output: String): Unit = { def test(result: Circuit, output: String): Unit = {
@@ -219,10 +222,14 @@ trait HasSimpleTestGenerator {
val lib_name = "awesome_lib_mem" val lib_name = "awesome_lib_mem"
val lib_addr_width = ceilLog2(libDepth) val lib_addr_width = ceilLog2(libDepth)
// Override these to change the port prefixes if needed.
def libPortPrefix: String = "lib"
def memPortPrefix: String = "outer"
// These generate "simple" SRAMs (1 masked read-write port) by default, // These generate "simple" SRAMs (1 masked read-write port) by default,
// but can be overridden if need be. // but can be overridden if need be.
def generateLibSRAM() = generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts) def generateLibSRAM() = generateSRAM(lib_name, libPortPrefix, libWidth, libDepth, libMaskGran, extraPorts)
def generateMemSRAM() = generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran) def generateMemSRAM() = generateSRAM(mem_name, memPortPrefix, memWidth, memDepth, memMaskGran)
val libSRAM = generateLibSRAM val libSRAM = generateLibSRAM
val memSRAM = generateMemSRAM val memSRAM = generateMemSRAM
@@ -245,17 +252,17 @@ trait HasSimpleTestGenerator {
def generateHeader(): String = { def generateHeader(): String = {
require (memSRAM.ports.size == 1, "Header generator only supports single port mem") require (memSRAM.ports.size == 1, "Header generator only supports single port mem")
val readEnable = if (memSRAM.ports(0).readEnable.isDefined) s"input outer_read_en : UInt<1>" else "" val readEnable = if (memSRAM.ports(0).readEnable.isDefined) s"input ${memPortPrefix}_read_en : UInt<1>" else ""
val headerMask = if (memHasMask) s"input outer_mask : UInt<${memMaskBits}>" else "" val headerMask = if (memHasMask) s"input ${memPortPrefix}_mask : UInt<${memMaskBits}>" else ""
s""" s"""
circuit $mem_name : circuit $mem_name :
module $mem_name : module $mem_name :
input outer_clk : Clock input ${memPortPrefix}_clk : Clock
input outer_addr : UInt<$mem_addr_width> input ${memPortPrefix}_addr : UInt<$mem_addr_width>
input outer_din : UInt<$memWidth> input ${memPortPrefix}_din : UInt<$memWidth>
output outer_dout : UInt<$memWidth> output ${memPortPrefix}_dout : UInt<$memWidth>
${readEnable} ${readEnable}
input outer_write_en : UInt<1> input ${memPortPrefix}_write_en : UInt<1>
${headerMask} ${headerMask}
""" """
} }
@@ -264,15 +271,15 @@ circuit $mem_name :
def generateFooterPorts(): String = { def generateFooterPorts(): String = {
require (libSRAM.ports.size == 1, "Footer generator only supports single port lib") require (libSRAM.ports.size == 1, "Footer generator only supports single port lib")
val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input lib_read_en : UInt<1>" else "" val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input ${libPortPrefix}_read_en : UInt<1>" else ""
val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else "" val footerMask = if (libHasMask) s"input ${libPortPrefix}_mask : UInt<${libMaskBits}>" else ""
s""" s"""
input lib_clk : Clock input ${libPortPrefix}_clk : Clock
input lib_addr : UInt<$lib_addr_width> input ${libPortPrefix}_addr : UInt<$lib_addr_width>
input lib_din : UInt<$libWidth> input ${libPortPrefix}_din : UInt<$libWidth>
output lib_dout : UInt<$libWidth> output ${libPortPrefix}_dout : UInt<$libWidth>
${readEnable} ${readEnable}
input lib_write_en : UInt<1> input ${libPortPrefix}_write_en : UInt<1>
${footerMask} ${footerMask}
""" """
} }
@@ -281,8 +288,8 @@ circuit $mem_name :
def generateFooter(): String = { def generateFooter(): String = {
require (libSRAM.ports.size == 1, "Footer generator only supports single port lib") require (libSRAM.ports.size == 1, "Footer generator only supports single port lib")
val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input lib_read_en : UInt<1>" else "" val readEnable = if (libSRAM.ports(0).readEnable.isDefined) s"input ${libPortPrefix}_read_en : UInt<1>" else ""
val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else "" val footerMask = if (libHasMask) s"input ${libPortPrefix}_mask : UInt<${libMaskBits}>" else ""
s""" s"""
extmodule $lib_name : extmodule $lib_name :
${generateFooterPorts} ${generateFooterPorts}