From 92a7e707502adfb8f8689d02c8c8c4b4e75eba59 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 17:42:05 -0700 Subject: [PATCH] fix rocketchip link --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 559431f2..2bf6a212 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ To get started using REBAR, see the documentation on the REBAR documentation sit REBAR is an open source starter template for your custom Chisel project. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -It contains processor cores ([Rocket][rocket], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC. +It contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC. REBAR is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. ## Resources