[Firechip] Add NIC endpoint; Add environments for all targets

generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala

@@ -3,12 +3,13 @@ package firesim.firesim
 import chisel3._
 import chisel3.experimental.RawModule
 
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 
 import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
+import icenet.HasPeripheryIceNICModuleImpValidOnly
 
 import junctions.{NastiKey, NastiParameters}
 import midas.widgets.{IsEndpoint, PeekPokeEndpoint}
@@ -26,11 +27,14 @@ import firesim.configs.MemModelKey
 // SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match
 // on the types rather than change trait code.
 
+case object NumNodes extends Field[Int](1)
+
 class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule {
   val clock = IO(Input(Clock()))
   val reset = WireInit(false.B)
   withClockAndReset(clock, reset) {
-    val target = Module(LazyModule(dutGen()).module)
+    // Instantiate multiple instances of the DUT to implement supernode
+    val targets = Seq.fill(p(NumNodes))(Module(LazyModule(dutGen()).module))
     val peekPokeEndpoint = PeekPokeEndpoint(reset)
     // A Seq of partial functions that will instantiate the right endpoint only
     // if that Mixin trait is present in the target's class instance
@@ -48,6 +52,7 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p
         Seq()
       },
       { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) },
+      { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) },
       { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) },
       { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) },
       { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp =>
@@ -66,7 +71,9 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p
       },
       { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) }
     )
-    // Apply each partial function to the DUT; collecting the generated endpoints
-    val endpoints = endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target))
+    // Apply each partial function to each DUT instance
+    for ((target) <- targets) {
+      endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target))
+    }
   }
 }

generators/firechip/src/main/scala/Targets.scala

@@ -60,6 +60,8 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(
     with HasTraceIOImp
     with CanHaveRocketMultiCycleRegfileImp
 
+class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)
+
 class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
     with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
@@ -110,6 +112,8 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu
     with ExcludeInvalidBoomAssertions
     with CanHaveBoomMultiCycleRegfileImp
 
+class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT)
+
 class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
     with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
@@ -133,46 +137,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub
     with ExcludeInvalidBoomAssertions
     with CanHaveBoomMultiCycleRegfileImp
 
-case object NumNodes extends Field[Int]
+class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT)
 
-class SupernodeIO(
-      nNodes: Int,
-      serialWidth: Int,
-      bagPrototype: HeterogeneousBag[midas.models.AXI4BundleWithEdge])(implicit p: Parameters)
-    extends Bundle {
-
-    val serial = Vec(nNodes, new SerialIO(serialWidth))
-    val mem_axi = Vec(nNodes, bagPrototype.cloneType)
-    val bdev = Vec(nNodes, new BlockDeviceIO)
-    val net = Vec(nNodes, new NICIOvonly)
-    val uart = Vec(nNodes, new UARTPortIO)
-
-    override def cloneType = new SupernodeIO(nNodes, serialWidth, bagPrototype).asInstanceOf[this.type]
-}
-
-
-class FireSimSupernodeDUT(implicit p: Parameters) extends Module {
-  val nNodes = p(NumNodes)
-  val nodes = Seq.fill(nNodes) {
-    Module(LazyModule(new FireSimDUT).module)
-  }
-
-  val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get))
-
-  io.mem_axi.zip(nodes.map(_.mem_axi4)).foreach {
-    case (out, mem_axi4) => out <> mem_axi4.get
-  }
-  io.serial <> nodes.map(_.serial)
-  io.bdev <> nodes.map(_.bdev)
-  io.net <> nodes.map(_.net)
-  io.uart <> nodes.map(_.uart(0))
-  nodes.foreach{ case n => {
-    n.debug.clockeddmi.get.dmi.req.valid := false.B
-    n.debug.clockeddmi.get.dmi.resp.ready := false.B
-    n.debug.clockeddmi.get.dmiClock := clock
-    n.debug.clockeddmi.get.dmiReset := reset.toBool
-    n.debug.clockeddmi.get.dmi.req.bits.data := DontCare
-    n.debug.clockeddmi.get.dmi.req.bits.addr := DontCare
-    n.debug.clockeddmi.get.dmi.req.bits.op := DontCare
-  } }
-}
+// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1
+class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)