From 40833f559dc94367265290787f91e085af5f770a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Jun 2023 16:34:03 -0700 Subject: [PATCH 01/20] Bump constellation to fix interconnect FIFO-fixers Constellation NoCs by-default do not preserve FIFO-ness. This bump makes the NoCs correctly report the lack of FIFO-ness, so the NoC buswrapper will correctly insert FIFOFixers to domains that should be FIFO --- generators/constellation | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/constellation b/generators/constellation index e9f1c828..8184e0e7 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62 +Subproject commit 8184e0e7e32ff11dce344c449158aa7551e164e0 From 4e5bb9c781e4c23d346337ee82b7b1ec6106c8ce Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 18:19:01 -0700 Subject: [PATCH 02/20] ADD: add ignore rule to vscode files --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index ac8e84d0..5dd75bec 100644 --- a/.gitignore +++ b/.gitignore @@ -27,3 +27,4 @@ project/project/ .ivy2 .sbt .classpath_cache/ +.vscode/ From 485dbcc4820e8cb7a7c0285cc7d653f809a28b15 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 18:19:34 -0700 Subject: [PATCH 03/20] ADD: add support for multiple peripherals of same kind --- .../fragments/PeripheralFragments.scala | 56 ++++++++++++++----- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 3b607ae0..3c9cc670 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -6,7 +6,8 @@ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} -import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} @@ -14,6 +15,7 @@ import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ import testchipip._ @@ -22,41 +24,65 @@ import chipyard.{ExtTLMem} // Set the bootrom to the Chipyard bootrom class WithBootROM extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) - .map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) + .map(_.copy( + address = 0x10000, + size = 0x10000, + hang = 0x10040, + contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" + )) }) // DOC include start: gpio config fragment -class WithGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Seq( - GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) +class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => { + case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( + GPIOParams(address = address, width = width, includeIOF = false)) }) // DOC include end: gpio config fragment -class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { - case PeripheryUARTKey => Seq( - UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) -}) - class WithNoUART extends Config((site, here, up) => { case PeripheryUARTKey => Nil }) +class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { + case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( + UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) +}) + class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) -class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { +class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below - case PeripherySPIFlashKey => Seq( - SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) + case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( + SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) +}) + +class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => { + case PeripherySPIKey => up(PeripherySPIKey) ++ Seq( + SPIParams(rAddress = address)) +}) + +class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => { + case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq( + I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing()) + ) +}) + +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None }) class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) -class WithNoDebug extends Config((site, here, up) => { - case DebugModuleKey => None +class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => { + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = idcodeVersion, + idcodePartNum = partNum, + idcodeManufId = manufId, + debugIdleCycles = debugIdleCycles) }) class WithTLBackingMemory extends Config((site, here, up) => { From c478d056e7532e00190b6eff49029749cac360ba Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 18:40:14 -0700 Subject: [PATCH 04/20] ADD: add documentation --- .../fragments/PeripheralFragments.scala | 61 ++++++++++++++++--- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 3c9cc670..6cfb49ce 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -21,28 +21,48 @@ import testchipip._ import chipyard.{ExtTLMem} -// Set the bootrom to the Chipyard bootrom -class WithBootROM extends Config((site, here, up) => { +/** + * Config fragment for adding a BootROM to the SoC + * + * @param address the address of the BootROM device + * @param size the size of the BootROM + * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset + * @param contentFileName the path to the BootROM image + */ +class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040, contentFileName: String = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img") extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) .map(_.copy( - address = 0x10000, - size = 0x10000, - hang = 0x10040, - contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" + address = address, + size = size, + hang = hand, + contentFileName = contentFileName )) }) -// DOC include start: gpio config fragment +/** + * Config fragment for adding a GPIO peripheral device to the SoC + * + * @param address the address of the GPIO device + * @param width the number of pins of the GPIO device + */ class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => { case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( GPIOParams(address = address, width = width, includeIOF = false)) }) -// DOC include end: gpio config fragment +/** + * Config fragment for removing all UART peripheral devices from the SoC + */ class WithNoUART extends Config((site, here, up) => { case PeripheryUARTKey => Nil }) +/** + * Config fragment for adding a UART peripheral device to the SoC + * + * @param address the address of the UART device + * @param baudrate the baudrate of the UART device + */ class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) @@ -52,17 +72,34 @@ class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) +/** + * Config fragment for adding a SPI peripheral device with Execute-in-Place capability to the SoC + * + * @param address the address of the SPI controller + * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory + * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory + */ class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) }) +/** + * Config fragment for adding a SPI peripheral device to the SoC + * + * @param address the address of the SPI controller + */ class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => { case PeripherySPIKey => up(PeripherySPIKey) ++ Seq( SPIParams(rAddress = address)) }) +/** + * Config fragment for adding a I2C peripheral device to the SoC + * + * @param address the address of the I2C controller + */ class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => { case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq( I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing()) @@ -77,6 +114,14 @@ class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) +/** + * Config fragment for adding a JTAG Debug Module to the SoC + * + * @param idcodeVersion the version of the JTAG protocol the Debug Module supports + * @param partNum the part number of the Debug Module + * @param manufId the 11-bit JEDEC Designer ID of the chip manufacturer + * @param debugIdleCycles the number of cycles the Debug Module waits before responding to a request + */ class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => { case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = idcodeVersion, From 8ddd8f6184b479719e5d0987da7397539cd27f06 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 19:13:19 -0700 Subject: [PATCH 05/20] FIX: fix typo --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 6cfb49ce..27f52c4d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -34,7 +34,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = .map(_.copy( address = address, size = size, - hang = hand, + hang = hang, contentFileName = contentFileName )) }) From 62825df3b9e6bc60f905becbacd2cf606b1e7283 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 13 Jun 2023 19:14:15 -0700 Subject: [PATCH 06/20] FIX: fix typo --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 27f52c4d..290e3dfe 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -29,13 +29,13 @@ import chipyard.{ExtTLMem} * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset * @param contentFileName the path to the BootROM image */ -class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040, contentFileName: String = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img") extends Config((site, here, up) => { +class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) .map(_.copy( address = address, size = size, hang = hang, - contentFileName = contentFileName + contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" )) }) From 8e39fe1fa1d8ae69e8b6be850220ac0c8472c15b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 14 Jun 2023 18:37:37 -0700 Subject: [PATCH 07/20] [ci skip] Fix broken docs link --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 290e3dfe..09636c49 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -39,6 +39,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = )) }) +// DOC include start: gpio config fragment /** * Config fragment for adding a GPIO peripheral device to the SoC * @@ -49,6 +50,7 @@ class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((si case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( GPIOParams(address = address, width = width, includeIOF = false)) }) +// DOC include end: gpio config fragment /** * Config fragment for removing all UART peripheral devices from the SoC From ccc77a02aab8cb351309eaad840095429a800593 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 15 Jun 2023 14:13:11 -0700 Subject: [PATCH 08/20] Revert "[ci skip] Fix broken docs link" This reverts commit 8e39fe1fa1d8ae69e8b6be850220ac0c8472c15b. --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 09636c49..290e3dfe 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -39,7 +39,6 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = )) }) -// DOC include start: gpio config fragment /** * Config fragment for adding a GPIO peripheral device to the SoC * @@ -50,7 +49,6 @@ class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((si case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( GPIOParams(address = address, width = width, includeIOF = false)) }) -// DOC include end: gpio config fragment /** * Config fragment for removing all UART peripheral devices from the SoC From cb24cf895585f168ef9b3b4cde793130014f2c84 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 15 Jun 2023 14:13:56 -0700 Subject: [PATCH 09/20] Revert "Merge pull request #1511 from ucb-bar/improve-peripheral" This reverts commit 4d8b3f9dbf9d8212a4509bb4b360d9b6075c23f6, reversing changes made to d287fed654d1d5f62d1ddae97b6c56956edf7dad. --- .gitignore | 1 - .../fragments/PeripheralFragments.scala | 109 +++--------------- 2 files changed, 19 insertions(+), 91 deletions(-) diff --git a/.gitignore b/.gitignore index 5dd75bec..ac8e84d0 100644 --- a/.gitignore +++ b/.gitignore @@ -27,4 +27,3 @@ project/project/ .ivy2 .sbt .classpath_cache/ -.vscode/ diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 290e3dfe..3b607ae0 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -6,8 +6,7 @@ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} -import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} @@ -15,119 +14,49 @@ import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ import testchipip._ import chipyard.{ExtTLMem} -/** - * Config fragment for adding a BootROM to the SoC - * - * @param address the address of the BootROM device - * @param size the size of the BootROM - * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset - * @param contentFileName the path to the BootROM image - */ -class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => { +// Set the bootrom to the Chipyard bootrom +class WithBootROM extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) - .map(_.copy( - address = address, - size = size, - hang = hang, - contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" - )) + .map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) }) -/** - * Config fragment for adding a GPIO peripheral device to the SoC - * - * @param address the address of the GPIO device - * @param width the number of pins of the GPIO device - */ -class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => { - case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( - GPIOParams(address = address, width = width, includeIOF = false)) +// DOC include start: gpio config fragment +class WithGPIO extends Config((site, here, up) => { + case PeripheryGPIOKey => Seq( + GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) +}) +// DOC include end: gpio config fragment + +class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { + case PeripheryUARTKey => Seq( + UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) }) -/** - * Config fragment for removing all UART peripheral devices from the SoC - */ class WithNoUART extends Config((site, here, up) => { case PeripheryUARTKey => Nil }) -/** - * Config fragment for adding a UART peripheral device to the SoC - * - * @param address the address of the UART device - * @param baudrate the baudrate of the UART device - */ -class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { - case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( - UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) -}) - class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) -/** - * Config fragment for adding a SPI peripheral device with Execute-in-Place capability to the SoC - * - * @param address the address of the SPI controller - * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory - * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory - */ -class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { +class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below - case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( - SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) -}) - -/** - * Config fragment for adding a SPI peripheral device to the SoC - * - * @param address the address of the SPI controller - */ -class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => { - case PeripherySPIKey => up(PeripherySPIKey) ++ Seq( - SPIParams(rAddress = address)) -}) - -/** - * Config fragment for adding a I2C peripheral device to the SoC - * - * @param address the address of the I2C controller - */ -class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => { - case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq( - I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing()) - ) -}) - -class WithNoDebug extends Config((site, here, up) => { - case DebugModuleKey => None + case PeripherySPIFlashKey => Seq( + SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) }) class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) -/** - * Config fragment for adding a JTAG Debug Module to the SoC - * - * @param idcodeVersion the version of the JTAG protocol the Debug Module supports - * @param partNum the part number of the Debug Module - * @param manufId the 11-bit JEDEC Designer ID of the chip manufacturer - * @param debugIdleCycles the number of cycles the Debug Module waits before responding to a request - */ -class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => { - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = idcodeVersion, - idcodePartNum = partNum, - idcodeManufId = manufId, - debugIdleCycles = debugIdleCycles) +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None }) class WithTLBackingMemory extends Config((site, here, up) => { From d99ffc9db217d0d526dc99eb20ac4eed5be5b65a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 15 Jun 2023 15:14:14 -0700 Subject: [PATCH 10/20] Bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 80e7376c..f13847e8 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 80e7376cf554ed302975d72ed091ac86a9e553e8 +Subproject commit f13847e839baee4a3c8d5d51e76a3dc9e9c1933f From 1fd672440c89d7d72cbf74a939904ec067bd01ae Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 16 Jun 2023 07:42:08 -0700 Subject: [PATCH 11/20] [ci skip] Update changelog for 1.10.0 --- CHANGELOG.md | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8e7ed003..3401cd43 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,89 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.10.0] - 2023-6-16 + +Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop + +### Added +* QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1399 +* New Scala-based Config Finder by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1424 +* ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1439 +* Add mt-helloworld example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1428 +* Add tutorial software by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1447 +* Support not instantiating the TileClockGater/ResetSetter PRCI control by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1459 +* ELF-based-loadmem | architectural restartable checkpoints by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1438 +* Add embench build support by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1479 +* Support multi-run of binaries by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1480 +* Integrate barf (prefetchers) by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1505 +* Add higher level explanations of RoCC + more resources by @nikhiljha in https://github.com/ucb-bar/chipyard/pull/1486 +* Support banked/partitioned scratchpads by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1431 +* Add dual-issue in-order "shuttle" core by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1495 +* Improve peripheral fragments to include more peripheral devices and support instantiating multiple instances of same device by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1511 + +### Changed +* Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1411 +* Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1430 +* PLL integration example + FlatChipTop/TestHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1427 +* bump testchipip by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1434 +* Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1436 +* Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1435 +* Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1446 +* Bump to Hammer 1.1.1 by @harrisonliew in https://github.com/ucb-bar/chipyard/pull/1451 +* Always initialize fpga-shells with init-submodules.sh by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1456 +* Support uni-directional TLSerdesser by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1476 +* Move xcelium.mk out of top-level by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1482 +* Set default config back to 1-channel by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1483 +* Unify supernode/harness-clocking across chipyard/firesim/fpga by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1474 +* Use fat jar's to remove SBT invocations by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1375 +* Bump to latest rocket-chip by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1475 +* Improvements to chipyard clocking by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1489 +* Downgrade cryptography | Pin linux sysroot by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1494 +* bump mempress by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1498 +* bump sha3 by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1499 +* Bump FireMarshal by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1502 +* Split NVDLA config out of ManyMMIOAccels config to reduce CI load by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1503 +* Ignore barstools compilation if not needed by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1504 +* Disable NVDLA simulations in CI by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1507 +* Update NoC example config to match new PRCI organization by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1509 +* Bump gemmini by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1519 + +### Fixed +* Various improvements and fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1420 +* Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1425 +* Clear screen on prompt by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1449 +* misc: many fixes to cospike by @tianrui-wei in https://github.com/ucb-bar/chipyard/pull/1450 +* Uniquify module names that are common to Top & Model by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1442 +* Use pk/encoding.h for hello/mt-hello by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1454 +* Fix no-uart configs by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1457 +* Fix support for no-bootROM systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1458 +* Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1460 +* uniquify module names by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1452 +* Flip serial_tl_clock to be generated off-chip by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1445 +* Move TestHarness to chipyard.harness, make chipyard/harness directory by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1463 +* Separate out conda-lock generation into new script by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1466 +* Bump DRAMSim2 to avoid verbose log files by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1468 +* Bump Verilator and use `TestDriver.v` as top by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1398 +* Add 1GB / 4GB DRAM firechip configs for FireSim VCU118 by @sagark in https://github.com/ucb-bar/chipyard/pull/1471 +* Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1465 +* Make BootAddrReg optional by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1464 +* Fix vcd/fst/fsdb waveform generation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1473 +* Switch RTL sims to absolute clock-generators by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1472 +* Generate objdump | check BINARY | cospike fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1467 +* Small QOL fixes for Xcelium by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1485 +* (VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus by @jerryhethatday in https://github.com/ucb-bar/chipyard/pull/1487 +* Force conda-lock to v1 by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1492 +* Loosen/tighten conda requirements | Fix conda-lock req by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1497 +* Misc Makefile Fixes by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1496 +* Bump constellation to fix interconnect FIFO-fixers by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1510 +* [ci skip] Fix broken docs link by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1515 +* Revert changes to peripheral fragments by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1518 + +### New Contributors +* @tianrui-wei made their first contribution in https://github.com/ucb-bar/chipyard/pull/1450 +* @jerryhethatday made their first contribution in https://github.com/ucb-bar/chipyard/pull/1487 +* @nikhiljha made their first contribution in https://github.com/ucb-bar/chipyard/pull/1486 + ## [1.9.1] - 2023-04-21 Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump From 21d2d93bec773bda1267313a3c2a5b619e2924c1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 16 Jun 2023 07:48:34 -0700 Subject: [PATCH 12/20] Bump firesim for 1.10.0 --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index b0007729..b0f276fb 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b0007729905bb3be4125440924ecc97bed9ecf88 +Subproject commit b0f276fba6ec0e32f3059fc850a7d34072bf29d3 From d98f423a967bfbe8581abf71970a31dcf78c2002 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Fri, 16 Jun 2023 07:53:48 -0700 Subject: [PATCH 13/20] Update CHANGELOG.md --- CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3401cd43..233ddbce 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,7 +4,7 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1. ## [1.10.0] - 2023-6-16 -Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop +Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop. FireSim bumped with new local FPGA support: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims. ### Added * QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1399 From 4f282afdc54233fba487164bf227df2b881df9e8 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Fri, 16 Jun 2023 09:41:53 -0700 Subject: [PATCH 14/20] Update build-setup.sh --- scripts/build-setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 02e1fd81..443ffabd 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -178,7 +178,7 @@ if run_step "6"; then pushd $CYDIR/sims/firesim ( echo $CYDIR - source sourceme-f1-manager.sh --skip-ssh-setup + source sourceme-manager.sh --skip-ssh-setup pushd sim make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim popd From 7c9fabfdef9733e118aaff54b9fc9bbb9908f2e0 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Fri, 16 Jun 2023 09:42:49 -0700 Subject: [PATCH 15/20] Update FPGA-Accelerated-Simulation.rst --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 703561fe..0e126252 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -26,9 +26,9 @@ Finally, source the following environment at the root of the FireSim directory: cd sims/firesim # (Recommended) The default manager environment (includes env.sh) - source sourceme-f1-manager.sh + source sourceme-manager.sh -.. Note:: Every time you want to use FireSim with a fresh shell, you must source this ``sourceme-f1-manager.sh`` +.. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh`` At this point you're ready to use FireSim with Chipyard. If you're not already familiar with FireSim, please return to the :fsim_doc:`FireSim Docs `, From de9d222d67434f51d24269a94059fcdda21baff4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vladimir=20Milovanovi=C4=87?= Date: Fri, 23 Jun 2023 21:07:35 +0200 Subject: [PATCH 16/20] Bump rocket-dsp-utils for TileLink memory master model fix. --- tools/rocket-dsp-utils | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index dcd9eb21..fe641d1c 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit dcd9eb212aefd8040cdf9c50adffbbf975422a1d +Subproject commit fe641d1c346d5605f95d235e8c75d0baac7fa6d8 From a5ed6ea038f51a8f9b3cfa1eb5b456bc9c6b6e70 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 29 Jun 2023 13:12:50 -0700 Subject: [PATCH 17/20] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 35d7e196..128ccb09 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 35d7e1969d1d3e54d29a10901737d9b2ba2ab5a3 +Subproject commit 128ccb09f0122651cadff4451cf30cf591636a70 From dcaca02e1488d99b93d101e07ec7edd6f6b5fb93 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jun 2023 15:04:04 -0700 Subject: [PATCH 18/20] small fixes for sim yaml generation --- vlsi/sim.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index b721c9fb..ea2c76d7 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -21,7 +21,7 @@ $(SIM_CONF): $(sim_common_files) check-binary done echo " options_meta: 'append'" >> $@ echo " defines:" >> $@ - for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ + for x in $(subst +define+,,$(SIM_PREPROC_DEFINES)); do \ echo ' - "'$$x'"' >> $@; \ done echo " defines_meta: 'append'" >> $@ @@ -75,7 +75,7 @@ $(SIM_TIMING_CONF): $(sim_common_files) echo "sim.inputs:" > $@ echo " defines: ['NTC']" >> $@ echo " defines_meta: 'append'" >> $@ - echo " timing_annotated: 'true'" >> $@ + echo " timing_annotated: true" >> $@ # Update hammer top-level sim targets to include our generated sim configs redo-sim-rtl: $(SIM_CONF) From 222059941ec2d6ad78a5b522a1f62a45809e43a0 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 30 Jun 2023 15:04:38 -0700 Subject: [PATCH 19/20] renamed clock_clock to clock_uncore_clock --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-designs/sky130-commercial.yml | 4 ++-- vlsi/example-designs/sky130-openroad-rockettile.yml | 2 +- vlsi/example-designs/sky130-openroad.yml | 2 +- vlsi/example-designs/sky130-rocket.yml | 2 +- vlsi/example-sky130.yml | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index dbcadab0..6fc819aa 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index ebc2d6a6..3f46a443 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index b2ecfb26..c4377d22 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,7 +2,7 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "30ns", uncertainty: "2ns"} + {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"} ] # Placement Constraints @@ -16,4 +16,4 @@ vlsi.inputs.clocks: [ # - path: "ChipTop" # ... # margins: -# right: 0 # or left: 0 \ No newline at end of file +# right: 0 # or left: 0 diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index 752facfd..a3fed011 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" vlsi.inputs.clocks: [ {name: "clock", period: "30ns", uncertainty: "3ns"} ] diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index b52266b4..669d2f92 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,7 +3,7 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_clock", period: "50ns", uncertainty: "2ns"} + {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"} ] # Flow parameters that yield a routable design with reasonable timing diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml index b03d26c5..2e7c7a5b 100644 --- a/vlsi/example-designs/sky130-rocket.yml +++ b/vlsi/example-designs/sky130-rocket.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" vlsi.inputs.clocks: [ {name: "clock", period: "5ns", uncertainty: "1ns"} ] diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 5481c4a8..1cd281f7 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "20ns", uncertainty: "1ns"} + {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow From a88d69b6030be1eda7e2a79f84e750c085b41e76 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 30 Jun 2023 22:28:17 -0700 Subject: [PATCH 20/20] Bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index f732ceb6..1a153d49 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f732ceb602bcccd4adb6a5f7137c7c0bea08be9d +Subproject commit 1a153d4974977a2d5f8baa9b4de51b3337d230fe