fixed merge conflict
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@@ -49,6 +49,7 @@ commands:
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- add_ssh_keys:
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fingerprints:
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- "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
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- "32:d6:89:d2:97:fa:db:de:a8:2d:2a:f2:70:dd:80:89"
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- checkout
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setup-tools:
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@@ -81,12 +82,15 @@ commands:
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build-script:
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type: string
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default: "do-rtl-build.sh"
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build-type:
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type: string
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default: "sim"
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steps:
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- setup-tools:
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tools-version: "<< parameters.tools-version >>"
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- run:
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name: Building << parameters.group-key >> subproject using Verilator
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command: .circleci/<< parameters.build-script >> << parameters.group-key >>
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command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >>
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no_output_timeout: << parameters.timeout >>
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- save_cache:
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key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }}
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@@ -367,6 +371,12 @@ jobs:
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project-key: "firesim-multiclock"
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run-script: "run-firesim-scala-tests.sh"
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timeout: "20m"
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prepare-chipyard-fpga:
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executor: main-env
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steps:
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- prepare-rtl:
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group-key: "group-fpga"
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build-type: "fpga"
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# Order and dependencies of jobs to run
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workflows:
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@@ -505,3 +515,8 @@ workflows:
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- install-riscv-toolchain
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- install-verilator
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- build-extra-tests
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# Prepare the fpga builds (just Verilog)
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- prepare-chipyard-fpga:
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requires:
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- install-riscv-toolchain
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