Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.

2020-09-17 13:43:28 -07:00
parent 2580073d75
commit 9135cda959
2 changed files with 5 additions and 5 deletions
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -26,7 +26,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
  val harnessClock = clock_32MHz
  val harnessReset = hReset
  val success = false.B
-  val dutReset = hReset
+  val dutReset = reset_core

  // must be after HasHarnessSignalReferences assignments
  ldut.harnessFunctions.foreach(_(this))