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Add Arty100T JTAG

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This commit is contained in:
Jerry Zhao
2023-12-20 08:43:35 -08:00
parent 81a2857ec7
commit 902d33ebd1
2 changed files with 25 additions and 2 deletions
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2
fpga/src/main/scala/arty100t/Configs.scala
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@@ -27,6 +27,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new WithArty100TPMODUART ++ new WithArty100TPMODUART ++
new WithArty100TUARTTSI ++ new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++ new WithArty100TDDRTL ++
new WithArty100TJTAG ++
new WithNoDesignKey ++ new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++ new testchipip.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithSerialTLTiedOff ++
@@ -39,7 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new chipyard.config.WithOffchipBusFrequency(freqMHz) ++ new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
new freechips.rocketchip.subsystem.WithoutTLMonitors) new freechips.rocketchip.subsystem.WithoutTLMonitors)

25
fpga/src/main/scala/arty100t/HarnessBinders.scala
View File

@@ -113,4 +113,27 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
}) })
// Maps the UART device to PMOD JD pins 3/7 // Maps the UART device to PMOD JD pins 3/7
class WithArty100TPMODUART extends WithArty100TUART("E2", "F4") class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
class WithArty100TJTAG extends HarnessBinder({
case (th: HasHarnessInstantiators, port: JTAGPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
harnessIO <> port.io
ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
ath.sdc.addGroup(clocks = Seq("JTCK"))
ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
val packagePinsWithPackageIOs = Seq(
("F4", IOPin(harnessIO.TCK)),
("D2", IOPin(harnessIO.TMS)),
("E2", IOPin(harnessIO.TDI)),
("D4", IOPin(harnessIO.TDO))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addPullup(io)
} }
}
})