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Add Arty100T JTAG

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This commit is contained in:
Jerry Zhao
2023-12-20 08:43:35 -08:00
parent 81a2857ec7
commit 902d33ebd1
2 changed files with 25 additions and 2 deletions
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25
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -113,4 +113,27 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
})
// Maps the UART device to PMOD JD pins 3/7
class WithArty100TPMODUART extends WithArty100TUART("E2", "F4")
class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
class WithArty100TJTAG extends HarnessBinder({
case (th: HasHarnessInstantiators, port: JTAGPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
harnessIO <> port.io
ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
ath.sdc.addGroup(clocks = Seq("JTCK"))
ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
val packagePinsWithPackageIOs = Seq(
("F4", IOPin(harnessIO.TCK)),
("D2", IOPin(harnessIO.TMS)),
("E2", IOPin(harnessIO.TDI)),
("D4", IOPin(harnessIO.TDO))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addPullup(io)
} }
}
})