[skip ci] make dco libs in example folder for consistency

2019-09-26 22:47:17 -07:00
parent e7e229a416
commit 8fffc1c670
5 changed files with 6 additions and 6 deletions
--- a/vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib
+++ b/vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib
@@ -0,0 +1,142 @@
+library (ExampleDCO_PVT_0P77V_0C) {
+    technology (cmos);
+    date : "Mon Sep  2 16:01:59 2019";
+    comment : "Generated by dotlibber.py";
+    revision : 0;
+    delay_model : table_lookup;
+    simulation : true;
+    capacitive_load_unit (1,pf);
+    voltage_unit : "1V";
+    current_unit : "1mA";
+    time_unit : "1ns";
+    pulling_resistance_unit : "1kohm";
+    nom_process : 1;
+    nom_temperature : 0;
+    nom_voltage : 0.770000;
+    voltage_map(VDD, 0.770000);
+    voltage_map(VSS, 0.000000);
+    operating_conditions("PVT_0P77V_0C") {
+        process : 1;
+        temperature : 0;
+        voltage : 0.770000;
+    }
+    default_operating_conditions : PVT_0P77V_0C;
+    lu_table_template (constraint_template_3x3) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1 ("0.0001, 0.0002, 0.0003");
+        index_2 ("0.0001, 0.0002, 0.0003");
+    }
+    lu_table_template (delay_template_8x8) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1 ("0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001");
+        index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
+    }
+
+
+    type (bus_13_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 14 ;
+        bit_from : 13 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+
+    type (bus_15_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 16 ;
+        bit_from : 15 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+
+    type (bus_7_to_0) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8 ;
+        bit_from : 7 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    cell (ExampleDCO) {
+        dont_use : true;
+        dont_touch : true;
+        is_macro_cell : true;
+
+        pg_pin (VDD) {
+            pg_type : primary_power;
+            voltage_name : VDD;
+        }
+
+        pg_pin (VSS) {
+            pg_type : primary_ground;
+            voltage_name : VSS;
+        }
+
+        pin (clock) {
+            direction : output;
+            clock : true;
+            max_capacitance : 0.02;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+
+        bus ( col_sel_b ) {
+            bus_type : bus_13_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.04;
+
+            pin ( col_sel_b[13:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        bus ( row_sel_b ) {
+            bus_type : bus_15_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.04;
+
+            pin ( row_sel_b[15:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        bus ( code_regulator ) {
+            bus_type : bus_7_to_0;
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.04;
+
+            pin ( code_regulator[7:0] ) {
+                related_power_pin : VDD;
+                related_ground_pin : VSS;
+            }
+        }
+
+        pin (dither) {
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.04;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+
+        pin (sleep_b) {
+            direction : input;
+            capacitance : 0.006;
+            max_transition : 0.04;
+            related_power_pin : VDD;
+            related_ground_pin : VSS;
+        }
+    }
+
+}