Fix annos (#53)
* Fixes #36 by using the renamemap * Also fix harness passes annotation handling h/t azidar * Remove old comment
This commit is contained in:
@@ -3,34 +3,48 @@
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package barstools.tapeout.transforms
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl._
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import firrtl.annotations.CircuitName
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import firrtl.annotations._
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import firrtl.ir._
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import firrtl.ir._
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import firrtl.passes.Pass
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import firrtl.passes.Pass
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// Converts some modules to external modules, based on a given function. If
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// Converts some modules to external modules, based on a given function. If
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// that function returns "true" then the module is converted into an ExtModule,
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// that function returns "true" then the module is converted into an ExtModule,
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// otherwise it's left alone.
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// otherwise it's left alone.
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class ConvertToExtModPass(classify: (Module) => Boolean) extends Pass {
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class ConvertToExtMod(classify: (Module) => Boolean) extends Transform {
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def run(c: Circuit): Circuit = {
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def inputForm = HighForm
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def outputForm = HighForm
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def run(state: CircuitState): (Circuit, RenameMap) = {
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val renames = RenameMap()
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val c = state.circuit
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renames.setCircuit(c.main)
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val modulesx = c.modules.map {
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val modulesx = c.modules.map {
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case m: ExtModule => m
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case m: ExtModule => m
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case m: Module =>
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case m: Module =>
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val removing = collection.mutable.HashSet[String]()
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def findDeadNames(statement: Statement): Unit = {
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statement match {
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case hn: IsDeclaration => removing += hn.name
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case x => x.foreachStmt(findDeadNames)
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}
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}
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if (classify(m)) {
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if (classify(m)) {
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m.foreachStmt(findDeadNames)
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removing.foreach { name =>
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renames.record(ReferenceTarget(c.main, m.name, Nil, name, Nil), Nil)
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}
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new ExtModule(m.info, m.name, m.ports, m.name, Seq.empty)
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new ExtModule(m.info, m.name, m.ports, m.name, Seq.empty)
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} else {
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} else {
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m
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m
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}
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}
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}
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}
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Circuit(c.info, modulesx, c.main)
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(Circuit(c.info, modulesx, c.main), renames)
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}
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}
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}
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class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with SeqTransformBased {
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def inputForm = HighForm
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def outputForm = HighForm
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def transforms = Seq(new ConvertToExtModPass(classify))
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def execute(state: CircuitState): CircuitState = {
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def execute(state: CircuitState): CircuitState = {
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val ret = runTransforms(state)
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val (ret, renames) = run(state)
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CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
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state.copy(circuit = ret, renames = Some(renames))
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}
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}
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}
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}
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@@ -5,21 +5,20 @@ package barstools.tapeout.transforms
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import firrtl._
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import firrtl._
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import firrtl.ir._
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import firrtl.ir._
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import firrtl.passes.Pass
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import firrtl.passes.Pass
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import firrtl.annotations._
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// "Re-Parents" a circuit, which changes the top module to something else.
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class ReParentCircuit(newTopName: String) extends Transform {
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class ReParentCircuitPass(newTopName: String) extends Pass {
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def run(c: Circuit): Circuit = {
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Circuit(c.info, c.modules, newTopName)
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}
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}
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class ReParentCircuit(newTopName: String) extends Transform with SeqTransformBased {
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def inputForm = HighForm
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def inputForm = HighForm
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def outputForm = HighForm
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def outputForm = HighForm
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def transforms = Seq(new ReParentCircuitPass(newTopName))
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def run(c: Circuit, newTopName: String): (Circuit, RenameMap) = {
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val myRenames = RenameMap()
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myRenames.record(CircuitTarget(c.main), CircuitTarget(newTopName))
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(Circuit(c.info, c.modules, newTopName), myRenames)
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}
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def execute(state: CircuitState): CircuitState = {
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def execute(state: CircuitState): CircuitState = {
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val ret = runTransforms(state)
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val (ret, renames) = run(state.circuit, newTopName)
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CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
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state.copy(circuit = ret, renames = Some(renames))
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}
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}
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}
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}
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@@ -5,7 +5,7 @@ package barstools.tapeout.transforms
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import firrtl._
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import firrtl._
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import firrtl.ir._
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import firrtl.ir._
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import firrtl.passes.Pass
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import firrtl.passes.Pass
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import firrtl.annotations.{SingleTargetAnnotation, Annotation}
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import firrtl.annotations._
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import firrtl.transforms.DontTouchAnnotation
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import firrtl.transforms.DontTouchAnnotation
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// Removes all the unused modules in a circuit by recursing through every
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// Removes all the unused modules in a circuit by recursing through every
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@@ -52,18 +52,9 @@ class RemoveUnusedModules extends Transform {
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val renames = state.renames.getOrElse(RenameMap())
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val renames = state.renames.getOrElse(RenameMap())
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// This is what the annotation filter should look like, but for some reason it doesn't work.
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state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Nil) }
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//state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Seq()) }
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val newCircuit = Circuit(state.circuit.info, usedModuleSeq, state.circuit.main)
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val newCircuit = Circuit(state.circuit.info, usedModuleSeq, state.circuit.main)
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val newAnnos = AnnotationSeq(state.annotations.toSeq.filter { _ match {
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state.copy(circuit = newCircuit, renames = Some(renames))
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// XXX This is wrong, but it works for now
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// Tracked by https://github.com/ucb-bar/barstools/issues/36
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case x: DontTouchAnnotation => false
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//case x: DontTouchAnnotation => usedModuleNames contains x.target.module
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case _ => true
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}})
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CircuitState(newCircuit, outputForm, newAnnos, Some(renames))
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}
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}
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}
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}
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