Fix annos (#53)

* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
This commit is contained in:
Colin Schmidt
2019-03-27 17:20:41 -07:00
committed by GitHub
parent affd033f0a
commit 8f7af5b0bf
3 changed files with 38 additions and 34 deletions

View File

@@ -3,34 +3,48 @@
package barstools.tapeout.transforms
import firrtl._
import firrtl.annotations.CircuitName
import firrtl.annotations._
import firrtl.ir._
import firrtl.passes.Pass
// Converts some modules to external modules, based on a given function. If
// that function returns "true" then the module is converted into an ExtModule,
// otherwise it's left alone.
class ConvertToExtModPass(classify: (Module) => Boolean) extends Pass {
def run(c: Circuit): Circuit = {
class ConvertToExtMod(classify: (Module) => Boolean) extends Transform {
def inputForm = HighForm
def outputForm = HighForm
def run(state: CircuitState): (Circuit, RenameMap) = {
val renames = RenameMap()
val c = state.circuit
renames.setCircuit(c.main)
val modulesx = c.modules.map {
case m: ExtModule => m
case m: Module =>
val removing = collection.mutable.HashSet[String]()
def findDeadNames(statement: Statement): Unit = {
statement match {
case hn: IsDeclaration => removing += hn.name
case x => x.foreachStmt(findDeadNames)
}
}
if (classify(m)) {
m.foreachStmt(findDeadNames)
removing.foreach { name =>
renames.record(ReferenceTarget(c.main, m.name, Nil, name, Nil), Nil)
}
new ExtModule(m.info, m.name, m.ports, m.name, Seq.empty)
} else {
m
}
}
Circuit(c.info, modulesx, c.main)
(Circuit(c.info, modulesx, c.main), renames)
}
}
class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with SeqTransformBased {
def inputForm = HighForm
def outputForm = HighForm
def transforms = Seq(new ConvertToExtModPass(classify))
def execute(state: CircuitState): CircuitState = {
val ret = runTransforms(state)
CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
val (ret, renames) = run(state)
state.copy(circuit = ret, renames = Some(renames))
}
}

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@@ -5,21 +5,20 @@ package barstools.tapeout.transforms
import firrtl._
import firrtl.ir._
import firrtl.passes.Pass
import firrtl.annotations._
// "Re-Parents" a circuit, which changes the top module to something else.
class ReParentCircuitPass(newTopName: String) extends Pass {
def run(c: Circuit): Circuit = {
Circuit(c.info, c.modules, newTopName)
}
}
class ReParentCircuit(newTopName: String) extends Transform with SeqTransformBased {
class ReParentCircuit(newTopName: String) extends Transform {
def inputForm = HighForm
def outputForm = HighForm
def transforms = Seq(new ReParentCircuitPass(newTopName))
def run(c: Circuit, newTopName: String): (Circuit, RenameMap) = {
val myRenames = RenameMap()
myRenames.record(CircuitTarget(c.main), CircuitTarget(newTopName))
(Circuit(c.info, c.modules, newTopName), myRenames)
}
def execute(state: CircuitState): CircuitState = {
val ret = runTransforms(state)
CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
val (ret, renames) = run(state.circuit, newTopName)
state.copy(circuit = ret, renames = Some(renames))
}
}

View File

@@ -5,7 +5,7 @@ package barstools.tapeout.transforms
import firrtl._
import firrtl.ir._
import firrtl.passes.Pass
import firrtl.annotations.{SingleTargetAnnotation, Annotation}
import firrtl.annotations._
import firrtl.transforms.DontTouchAnnotation
// Removes all the unused modules in a circuit by recursing through every
@@ -52,18 +52,9 @@ class RemoveUnusedModules extends Transform {
val renames = state.renames.getOrElse(RenameMap())
// This is what the annotation filter should look like, but for some reason it doesn't work.
//state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Seq()) }
state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Nil) }
val newCircuit = Circuit(state.circuit.info, usedModuleSeq, state.circuit.main)
val newAnnos = AnnotationSeq(state.annotations.toSeq.filter { _ match {
// XXX This is wrong, but it works for now
// Tracked by https://github.com/ucb-bar/barstools/issues/36
case x: DontTouchAnnotation => false
//case x: DontTouchAnnotation => usedModuleNames contains x.target.module
case _ => true
}})
CircuitState(newCircuit, outputForm, newAnnos, Some(renames))
state.copy(circuit = newCircuit, renames = Some(renames))
}
}