diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index eeb26b60..e86140eb 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -30,7 +30,8 @@ class WithArtyTweaks extends Config( new chipyard.config.WithFrontBusFrequency(32) ++ new chipyard.config.WithControlBusFrequency(32) ++ new chipyard.config.WithPeripheryBusFrequency(32) ++ - new testchipip.serdes.WithNoSerialTL + new testchipip.serdes.WithNoSerialTL ++ + new testchipip.soc.WithNoScratchpads ) class TinyRocketArtyConfig extends Config( diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index c9892aa8..d5c83af3 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -21,9 +21,13 @@ class WithNoDesignKey extends Config((site, here, up) => { case DesignKey => (p: Parameters) => new SimpleLazyModule()(p) }) +// By default, this uses the on-board USB-UART for the TSI-over-UART link +// The PMODUART HarnessBinder maps the actual UART device to JD pin class WithArty100TTweaks(freqMHz: Double = 50) extends Config( + new WithArty100TPMODUART ++ new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ + new WithArty100TJTAG ++ new WithNoDesignKey ++ new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ @@ -36,8 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( new chipyard.config.WithOffchipBusFrequency(freqMHz) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.config.WithNoDebug ++ // no jtag - new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY new freechips.rocketchip.subsystem.WithoutTLMonitors) diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index a535e65f..577bd1b2 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -33,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell harnessSysPLLNode := clockOverlay.overlayOutput.node - val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0)))) - val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay] val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( name = "chip_ddr", diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index dd7c1a35..072b900e 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -23,7 +23,17 @@ import chipyard.iobinders._ class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] - ath.io_uart_bb.bundle <> port.io.uart + val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi") + harnessIO <> port.io.uart + val packagePinsWithPackageIOs = Seq( + ("A9" , IOPin(harnessIO.rxd)), + ("D10", IOPin(harnessIO.txd))) + packagePinsWithPackageIOs foreach { case (pin, io) => { + ath.xdc.addPackagePin(io, pin) + ath.xdc.addIOStandard(io, "LVCMOS33") + ath.xdc.addIOB(io) + } } + ath.other_leds(1) := port.io.dropped ath.other_leds(9) := port.io.tsi2tl_state(0) ath.other_leds(10) := port.io.tsi2tl_state(1) @@ -32,6 +42,7 @@ class WithArty100TUARTTSI extends HarnessBinder({ } }) + class WithArty100TDDRTL extends HarnessBinder({ case (th: HasHarnessInstantiators, port: TLMemPort) => { val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] @@ -81,3 +92,46 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ artyTh.xdc.clockDedicatedRouteFalse(clkIO) } }) + +// Maps the UART device to the on-board USB-UART +class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: UARTPort) => { + val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart") + harnessIO <> port.io + val packagePinsWithPackageIOs = Seq( + (rxdPin, IOPin(harnessIO.rxd)), + (txdPin, IOPin(harnessIO.txd))) + packagePinsWithPackageIOs foreach { case (pin, io) => { + ath.xdc.addPackagePin(io, pin) + ath.xdc.addIOStandard(io, "LVCMOS33") + ath.xdc.addIOB(io) + } } + } +}) + +// Maps the UART device to PMOD JD pins 3/7 +class WithArty100TPMODUART extends WithArty100TUART("G2", "F3") + +class WithArty100TJTAG extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: JTAGPort) => { + val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag") + harnessIO <> port.io + + ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10) + ath.sdc.addGroup(clocks = Seq("JTCK")) + ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK)) + val packagePinsWithPackageIOs = Seq( + ("F4", IOPin(harnessIO.TCK)), + ("D2", IOPin(harnessIO.TMS)), + ("E2", IOPin(harnessIO.TDI)), + ("D4", IOPin(harnessIO.TDO)) + ) + packagePinsWithPackageIOs foreach { case (pin, io) => { + ath.xdc.addPackagePin(io, pin) + ath.xdc.addIOStandard(io, "LVCMOS33") + ath.xdc.addPullup(io) + } } + } +}) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index cef46e04..775ecb58 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -69,6 +69,8 @@ class AbstractConfig extends Config( width = 32 // serial-tilelink interface with 32 lanes ) )) ++ + new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad + size = 64 * 1024) ++ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 66cb1aa2..4288fa84 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -146,7 +146,7 @@ class MultiNoCConfig extends Config( * L2 3 | MI | Cache[3] | 6 * DRAM 0 | MO | system[0] | 3 * DRAM 1 | MO | system[1] | 5 - * extram | MO | serial_tl_0 | 9 + * spad | MO | ram[0] | 9 */ // DOC include start: SharedNoCConfig class SharedNoCConfig extends Config( @@ -169,7 +169,7 @@ class SharedNoCConfig extends Config( "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6), outNodeMapping = ListMap( "system[0]" -> 3, "system[1]" -> 5, - "serial_tl_0" -> 9)) + "ram[0]" -> 9)) )) ++ new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 4f70f9ee..6647e516 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -4,6 +4,7 @@ import org.chipsalliance.cde.config.{Config} // A empty config with no cores. Useful for testing class NoCoresConfig extends Config( + new testchipip.soc.WithNoScratchpads ++ new testchipip.boot.WithNoBootAddrReg ++ new testchipip.boot.WithNoCustomBootPin ++ new chipyard.config.WithNoCLINT ++ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 929e8c59..216cb53e 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -12,7 +12,8 @@ class RocketConfig extends Config( new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( - new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports + new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports + new testchipip.soc.WithNoScratchpads ++ // All memory is the Rocket TCMs new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory @@ -36,6 +37,7 @@ class RV32RocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( new chipyard.config.WithL2TLBs(0) ++ + new testchipip.soc.WithNoScratchpads ++ // remove subsystem scratchpads, confusingly named, does not remove the L1D$ scratchpads new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 7d7c7ac3..2edda3ce 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -7,6 +7,7 @@ import org.chipsalliance.cde.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ + new testchipip.soc.WithNoScratchpads ++ // No scratchpads new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config( class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new testchipip.soc.WithNoScratchpads ++ // No scratchpads new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config( class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new testchipip.soc.WithNoScratchpads ++ // No scratchpads new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config( class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new testchipip.soc.WithNoScratchpads ++ // No scratchpads new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config( class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new testchipip.soc.WithNoScratchpads ++ // No scratchpads new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config( class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new testchipip.soc.WithNoScratchpads ++ // No scratchpads new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 45f72641..7695be70 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -116,7 +116,10 @@ object GetSystemParameters { } class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString))) + case IOBinders => { + val upMap = up(IOBinders) + upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString))) + } }) class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T]( diff --git a/generators/testchipip b/generators/testchipip index 70e19831..c13b8f65 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 70e198313a7e467f9219e4caba0158a96f851503 +Subproject commit c13b8f658b955f9f61a52caefcd6388e034b0575 diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 9d79735a..d3a66ca6 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -29,7 +29,8 @@ usage() { echo " 7. FireSim pre-compile sources" echo " 8. FireMarshal" echo " 9. FireMarshal pre-compile default buildroot Linux sources" - echo " 10. Runs repository clean-up" + echo " 10. Install CIRCT" + echo " 11. Runs repository clean-up" echo "" echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**" echo "" @@ -152,16 +153,6 @@ if run_step "1"; then conda activate $CYDIR/.conda-env exit_if_last_command_failed - # install circt into conda - git submodule update --init $CYDIR/tools/install-circt && - $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \ - -f circt-full-shared-linux-x64.tar.gz \ - -i $CONDA_PREFIX \ - -v version-file \ - -x $CYDIR/conda-reqs/circt.json \ - -g null - exit_if_last_command_failed - # Conda Setup # Provide a sourceable snippet that can be used in subshells that may not have # inhereted conda functions that would be brought in under a login shell that @@ -273,8 +264,31 @@ if run_step "8"; then popd fi -# do misc. cleanup for a "clean" git status if run_step "10"; then + # install circt into conda + if run_step "1"; then + PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE + else + if [ -z "$RISCV" ] ; then + error "ERROR: If conda initialization skipped, \$RISCV variable must be defined." + exit 1 + fi + PREFIX=$RISCV + fi + + git submodule update --init $CYDIR/tools/install-circt && + $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \ + -f circt-full-shared-linux-x64.tar.gz \ + -i $PREFIX \ + -v version-file \ + -x $CYDIR/conda-reqs/circt.json \ + -g null + exit_if_last_command_failed +fi + + +# do misc. cleanup for a "clean" git status +if run_step "11"; then begin_step "10" "Cleaning up repository" $CYDIR/scripts/repo-clean.sh exit_if_last_command_failed