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Use DigitalTop in Platform | Use Chipyard BootRom

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This commit is contained in:
abejgonzalez
2020-09-04 18:55:56 -07:00
parent 990362933d
commit 8eb807a2fd
8 changed files with 39 additions and 178 deletions
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30
fpga/Makefile
View File

@@ -21,9 +21,9 @@ SUB_PROJECT := fpga
SBT_PROJECT := freedomPlatforms SBT_PROJECT := freedomPlatforms
MODEL := E300ArtyDevKitFPGAChip MODEL := E300ArtyDevKitFPGAChip
VLOG_MODEL := E300ArtyDevKitFPGAChip VLOG_MODEL := E300ArtyDevKitFPGAChip
MODEL_PACKAGE := sifive.freedom.everywhere.e300artydevkit MODEL_PACKAGE := chipyard.fpga
CONFIG := E300ArtyDevKitConfig CONFIG := E300ArtyDevKitConfig
CONFIG_PACKAGE := sifive.freedom.everywhere.e300artydevkit CONFIG_PACKAGE := chipyard.fpga
GENERATOR_PACKAGE := chipyard GENERATOR_PACKAGE := chipyard
TB := none # unused TB := none # unused
TOP := E300ArtyDevKitPlatform TOP := E300ArtyDevKitPlatform
@@ -34,7 +34,6 @@ BOARD ?= arty
######################################################################################### #########################################################################################
# misc. directories # misc. directories
######################################################################################### #########################################################################################
bootrom_dir := $(base_dir)/fpga/bootrom/xip
fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx
fpga_common_script_dir := $(fpga_dir)/common/tcl fpga_common_script_dir := $(fpga_dir)/common/tcl
@@ -49,27 +48,7 @@ include $(base_dir)/common.mk
all_vsrcs := \ all_vsrcs := \
$(sim_vsrcs) \ $(sim_vsrcs) \
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \ $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
$(build_dir)/$(long_name).rom.v
#########################################################################################
# build rom for the fpga
#########################################################################################
# needed for bootrom makefile
export BUILD_DIR=$(build_dir)
export ROCKETCHIP_DIR
export LONG_NAME=$(long_name)
export ROMCONF=$(build_dir)/$(long_name).rom.conf
romgen := $(build_dir)/$(long_name).rom.v
$(romgen): $(sim_vsrcs)
ifneq ($(bootrom_dir),"")
$(MAKE) -C $(bootrom_dir) romgen
mv $(build_dir)/rom.v $@
endif
.PHONY: romgen
romgen: $(romgen)
######################################################################################### #########################################################################################
# vivado rules # vivado rules
@@ -119,6 +98,3 @@ prjx: $(prjx)
.PHONY: clean .PHONY: clean
clean: clean:
rm -rf $(gen_dir) rm -rf $(gen_dir)
ifneq ($(bootrom_dir),"")
$(MAKE) -C $(bootrom_dir) clean
endif

50
fpga/bootrom/xip/Makefile
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@@ -1,50 +0,0 @@
# RISCV environment variable must be set
# needs the following variables
# LONG_NAME
# BUILD_DIR
# ROCKETCHIP_DIR
# ROMCONF
CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
LFLAGS=-static -nostdlib
dtb := $(BUILD_DIR)/$(LONG_NAME).dtb
$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts
dtc -I dts -O dtb -o $@ $<
.PHONY: dtb
dtb: $(dtb)
elf := $(BUILD_DIR)/xip.elf
$(elf): xip.S $(dtb)
$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
.PHONY: elf
elf: $(elf)
bin := $(BUILD_DIR)/xip.bin
$(bin): $(elf)
$(OBJCOPY) -O binary $< $@
.PHONY: bin
bin: $(bin)
hex := $(BUILD_DIR)/xip.hex
$(hex): $(bin)
od -t x4 -An -w4 -v $< > $@
.PHONY: hex
hex: $(hex)
romgen := $(BUILD_DIR)/rom.v
$(romgen): $(hex)
$(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
.PHONY: romgen
romgen: $(romgen)
.PHONY: clean
clean::
rm -rf $(hex) $(elf)

16
fpga/bootrom/xip/xip.S
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@@ -1,16 +0,0 @@
// See LICENSE for license details.
// Execute in place
// Jump directly to XIP_TARGET_ADDR
.section .text.init
.option norvc
.globl _start
_start:
csrr a0, mhartid
la a1, dtb
li t0, XIP_TARGET_ADDR
jr t0
.section .rodata
dtb:
.incbin DEVICE_TREE

47
fpga/src/main/scala/arty/Config.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit package chipyard.fpga
import freechips.rocketchip.config._ import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
@@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._ import sifive.blocks.devices.i2c._
// Default FreedomEConfig class E300DevKitExtra extends Config((site, here, up) => {
class DefaultFreedomEConfig extends Config (
new WithNBreakpoints(2) ++
new WithNExtTopInterrupts(0) ++
new WithJtagDTM ++
new TinyConfig
)
// Freedom E300 Arty Dev Kit Peripherals
class E300DevKitPeripherals extends Config((site, here, up) => {
case PeripheryGPIOKey => List( case PeripheryGPIOKey => List(
GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
case PeripheryPWMKey => List( case PeripheryPWMKey => List(
@@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => {
I2CParams(address = 0x10016000)) I2CParams(address = 0x10016000))
case PeripheryMockAONKey => case PeripheryMockAONKey =>
MockAONParams(address = 0x10000000) MockAONParams(address = 0x10000000)
case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM")) case DTSTimebase => BigInt(32768)
case BootROMLocated(InSubsystem) => None case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2,
idcodePartNum = 0x000,
idcodeManufId = 0x489,
debugIdleCycles = 5)
}) })
// Freedom E300 Arty Dev Kit Peripherals
class E300ArtyDevKitConfig extends Config( class E300ArtyDevKitConfig extends Config(
new E300DevKitPeripherals ++ new E300DevKitExtra ++
new DefaultFreedomEConfig().alter((site,here,up) => { new chipyard.config.WithBootROM ++
case DTSTimebase => BigInt(32768) new chipyard.config.WithL2TLBs(1024) ++
case JtagDTMKey => new JtagDTMConfig ( new freechips.rocketchip.subsystem.With1TinyCore ++
idcodeVersion = 2, new freechips.rocketchip.subsystem.WithNBanks(0) ++
idcodePartNum = 0x000, new freechips.rocketchip.subsystem.WithNoMemPort ++
idcodeManufId = 0x489, new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
debugIdleCycles = 5) new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
}) new freechips.rocketchip.subsystem.WithJtagDTM ++
) new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

2
fpga/src/main/scala/arty/FPGAChip.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit package chipyard.fpga
import Chisel._ import Chisel._
import chisel3.core.{attach} import chisel3.core.{attach}

7
fpga/src/main/scala/arty/Platform.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit package chipyard.fpga
import Chisel._ import Chisel._
@@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._ import sifive.blocks.devices.i2c._
import sifive.blocks.devices.pinctrl._ import sifive.blocks.devices.pinctrl._
import chipyard.{DigitalTop}
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
// PinGen // PinGen
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
@@ -51,8 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
//------------------------------------------------------------------------- //-------------------------------------------------------------------------
class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
//val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop? val sys = Module(LazyModule(new DigitalTop).module)
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
val io = new E300ArtyDevKitPlatformIO val io = new E300ArtyDevKitPlatformIO
// This needs to be de-asserted synchronously to the coreClk. // This needs to be de-asserted synchronously to the coreClk.

57
fpga/src/main/scala/arty/System.scala
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@@ -1,57 +0,0 @@
// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.system._
import sifive.blocks.devices.mockaon._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
//-------------------------------------------------------------------------
// E300ArtyDevKitSystem
//-------------------------------------------------------------------------
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
with HasPeripheryDebug
with HasPeripheryMockAON
with chipyard.example.CanHavePeripheryGCD
with HasPeripheryUART
with HasPeripherySPIFlash
with HasPeripherySPI
with HasPeripheryGPIO
with HasPeripheryPWM
with HasPeripheryI2C {
val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]()
tileResetVectorNexusNode := maskROMResetVectorSourceNode
override lazy val module = new E300ArtyDevKitSystemModule(this)
}
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
extends RocketSubsystemModuleImp(_outer)
with HasPeripheryDebugModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with HasPeripheryUARTModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp
with HasPeripherySPIFlashModuleImp
with HasPeripheryMockAONModuleImp
with HasPeripheryPWMModuleImp
with HasPeripheryI2CModuleImp {
// connect reset vector to 1st MaskROM
_outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U
}

8
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -13,6 +13,10 @@ import freechips.rocketchip.devices.tilelink._
// DOC include start: DigitalTop // DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with sifive.blocks.devices.mockaon.HasPeripheryMockAON
with sifive.blocks.devices.spi.HasPeripherySPI
with sifive.blocks.devices.pwm.HasPeripheryPWM
with sifive.blocks.devices.i2c.HasPeripheryI2C
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
@@ -31,6 +35,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
} }
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp with testchipip.CanHavePeripherySerialModuleImp