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Use DigitalTop in Platform | Use Chipyard BootRom

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This commit is contained in:
abejgonzalez
2020-09-04 18:55:56 -07:00
parent 990362933d
commit 8eb807a2fd
8 changed files with 39 additions and 178 deletions
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47
fpga/src/main/scala/arty/Config.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
package chipyard.fpga
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
@@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
// Default FreedomEConfig
class DefaultFreedomEConfig extends Config (
new WithNBreakpoints(2) ++
new WithNExtTopInterrupts(0) ++
new WithJtagDTM ++
new TinyConfig
)
// Freedom E300 Arty Dev Kit Peripherals
class E300DevKitPeripherals extends Config((site, here, up) => {
class E300DevKitExtra extends Config((site, here, up) => {
case PeripheryGPIOKey => List(
GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
case PeripheryPWMKey => List(
@@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => {
I2CParams(address = 0x10016000))
case PeripheryMockAONKey =>
MockAONParams(address = 0x10000000)
case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM"))
case BootROMLocated(InSubsystem) => None
case DTSTimebase => BigInt(32768)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2,
idcodePartNum = 0x000,
idcodeManufId = 0x489,
debugIdleCycles = 5)
})
// Freedom E300 Arty Dev Kit Peripherals
class E300ArtyDevKitConfig extends Config(
new E300DevKitPeripherals ++
new DefaultFreedomEConfig().alter((site,here,up) => {
case DTSTimebase => BigInt(32768)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2,
idcodePartNum = 0x000,
idcodeManufId = 0x489,
debugIdleCycles = 5)
})
)
new E300DevKitExtra ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.With1TinyCore ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithJtagDTM ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

2
fpga/src/main/scala/arty/FPGAChip.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
package chipyard.fpga
import Chisel._
import chisel3.core.{attach}

7
fpga/src/main/scala/arty/Platform.scala
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@@ -1,5 +1,5 @@
// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
package chipyard.fpga
import Chisel._
@@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.pinctrl._
import chipyard.{DigitalTop}
//-------------------------------------------------------------------------
// PinGen
//-------------------------------------------------------------------------
@@ -51,8 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
//-------------------------------------------------------------------------
class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
//val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop?
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
val sys = Module(LazyModule(new DigitalTop).module)
val io = new E300ArtyDevKitPlatformIO
// This needs to be de-asserted synchronously to the coreClk.

57
fpga/src/main/scala/arty/System.scala
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@@ -1,57 +0,0 @@
// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.system._
import sifive.blocks.devices.mockaon._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
//-------------------------------------------------------------------------
// E300ArtyDevKitSystem
//-------------------------------------------------------------------------
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
with HasPeripheryDebug
with HasPeripheryMockAON
with chipyard.example.CanHavePeripheryGCD
with HasPeripheryUART
with HasPeripherySPIFlash
with HasPeripherySPI
with HasPeripheryGPIO
with HasPeripheryPWM
with HasPeripheryI2C {
val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]()
tileResetVectorNexusNode := maskROMResetVectorSourceNode
override lazy val module = new E300ArtyDevKitSystemModule(this)
}
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
extends RocketSubsystemModuleImp(_outer)
with HasPeripheryDebugModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with HasPeripheryUARTModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp
with HasPeripherySPIFlashModuleImp
with HasPeripheryMockAONModuleImp
with HasPeripheryPWMModuleImp
with HasPeripheryI2CModuleImp {
// connect reset vector to 1st MaskROM
_outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U
}