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Merge pull request #1278 from Lorilandly/vc707fpga

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Add support for VC707 FPGA board changelog:added
This commit is contained in:
Abraham Gonzalez
2022-12-14 19:16:49 -08:00
committed by GitHub
parent cb56f8f8f9 5c55614115
commit 8e851b0285
13 changed files with 378 additions and 51 deletions
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3
.github/scripts/defaults.sh vendored
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@@ -31,7 +31,7 @@ grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation"
grouping["group-fpga"]="arty vcu118"
grouping["group-fpga"]="arty vcu118 vc707"
# key value store to get the build strings
declare -A mapping
@@ -71,3 +71,4 @@ mapping["testchipip"]="SUB_PROJECT=testchipip"
mapping["arty"]="SUB_PROJECT=arty verilog"
mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
mapping["vc707"]="SUB_PROJECT=vc707 verilog"