wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #968 from duyhieubui/master

Browse Source 
Fixes UART portmap for Arty.
This commit is contained in:
James Dunn
2021-10-13 13:25:10 -07:00
committed by GitHub
parent 21a44d7596 d9858c1dc8
commit 8e59db02fd
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/src/main/scala/arty/HarnessBinders.scala
View File

@@ -72,8 +72,8 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) { withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_txd_in, ports.head.txd) IOBUF(th.uart_rxd_out, ports.head.txd)
ports.head.rxd := IOBUF(th.uart_rxd_out) ports.head.rxd := IOBUF(th.uart_txd_in)
} }
} }
}) })