From fc3a3eabff12b28dac417027dc3da62f9838876f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 21 Oct 2020 21:08:51 +0000 Subject: [PATCH 1/3] Update MacroCompiler for Chisel 3.4 --- macros/src/main/scala/MacroCompiler.scala | 26 +++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala index cb24bc9c..53d17847 100644 --- a/macros/src/main/scala/MacroCompiler.scala +++ b/macros/src/main/scala/MacroCompiler.scala @@ -23,6 +23,14 @@ import Utils._ case class MacroCompilerException(msg: String) extends Exception(msg) +// TODO The parameters could be unpacked here instead of keeping it in a serialized form +case class MacroCompilerAnnotation(content: String) extends NoTargetAnnotation { + import MacroCompilerAnnotation.Params + + def params: Params = MacroCompilerUtil.objFromString(content).asInstanceOf[Params] +} + + /** * The MacroCompilerAnnotation to trigger the macro compiler. * Note that this annotation does NOT actually target any modules for @@ -32,7 +40,6 @@ case class MacroCompilerException(msg: String) extends Exception(msg) * To use, simply annotate the entire circuit itself with this annotation and * include [[MacroCompilerTransform]]. * - * TODO: make this into a "true" annotation? */ object MacroCompilerAnnotation { /** Macro compiler mode. */ @@ -92,16 +99,9 @@ object MacroCompilerAnnotation { * @param c Top-level circuit name (see class description) * @param p Parameters (see above). */ - def apply(c: String, p: Params): Annotation = - Annotation(CircuitName(c), classOf[MacroCompilerTransform], MacroCompilerUtil.objToString(p)) + def apply(c: String, p: Params): MacroCompilerAnnotation = + MacroCompilerAnnotation(MacroCompilerUtil.objToString(p)) - def unapply(a: Annotation) = a match { - case Annotation(CircuitName(c), t, serialized) if t == classOf[MacroCompilerTransform] => { - val p: Params = MacroCompilerUtil.objFromString(serialized).asInstanceOf[Params] - Some(c, p) - } - case _ => None - } } class MacroCompilerPass(mems: Option[Seq[Macro]], @@ -656,9 +656,9 @@ class MacroCompilerTransform extends Transform { def inputForm = MidForm def outputForm = MidForm - def execute(state: CircuitState) = getMyAnnotations(state) match { - case Seq(MacroCompilerAnnotation(state.circuit.main, - MacroCompilerAnnotation.Params(memFile, memFileFormat, libFile, hammerIR, costMetric, mode, useCompiler, forceCompile, forceSynflops))) => + def execute(state: CircuitState) = state.annotations match { + case Seq(anno: MacroCompilerAnnotation) => + val MacroCompilerAnnotation.Params(memFile, memFileFormat, libFile, hammerIR, costMetric, mode, useCompiler, forceCompile, forceSynflops) = anno.params if (mode == MacroCompilerAnnotation.FallbackSynflops) { throw new UnsupportedOperationException("Not implemented yet") } From aca4bd579f03acf5a06add2de5b005cdfa6c25ec Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 23 Oct 2020 18:01:06 +0000 Subject: [PATCH 2/3] update build.sbt for Chisel3.4/FIRRTL1.4 --- build.sbt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index 9ec44bf7..fa76c325 100644 --- a/build.sbt +++ b/build.sbt @@ -1,8 +1,8 @@ // See LICENSE for license details. val defaultVersions = Map( - "chisel3" -> "3.2-SNAPSHOT", - "chisel-iotesters" -> "1.3-SNAPSHOT" + "chisel3" -> "3.4.0", + "chisel-iotesters" -> "1.5.0" ) lazy val commonSettings = Seq( @@ -31,7 +31,7 @@ lazy val macros = (project in file("macros")) .settings(commonSettings) .settings(Seq( libraryDependencies ++= Seq( - "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT" % Test + "edu.berkeley.cs" %% "firrtl-interpreter" % "1.4.0" % Test ), mainClass := Some("barstools.macros.MacroCompiler") )) From 446cb84cbfe9b776d62ab4dcef0075c4a645723b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 23 Oct 2020 18:02:35 +0000 Subject: [PATCH 3/3] fixup! Update MacroCompiler for Chisel 3.4 Need to collect the annotations into a Seq. Also updated the macros project tests. --- macros/src/main/scala/MacroCompiler.scala | 2 +- macros/src/test/scala/MacroCompilerSpec.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala index 53d17847..c057baa6 100644 --- a/macros/src/main/scala/MacroCompiler.scala +++ b/macros/src/main/scala/MacroCompiler.scala @@ -656,7 +656,7 @@ class MacroCompilerTransform extends Transform { def inputForm = MidForm def outputForm = MidForm - def execute(state: CircuitState) = state.annotations match { + def execute(state: CircuitState) = state.annotations.collect { case a: MacroCompilerAnnotation => a } match { case Seq(anno: MacroCompilerAnnotation) => val MacroCompilerAnnotation.Params(memFile, memFileFormat, libFile, hammerIR, costMetric, mode, useCompiler, forceCompile, forceSynflops) = anno.params if (mode == MacroCompilerAnnotation.FallbackSynflops) { diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala index dfecc0c1..488f68fe 100644 --- a/macros/src/test/scala/MacroCompilerSpec.scala +++ b/macros/src/test/scala/MacroCompilerSpec.scala @@ -3,7 +3,7 @@ package barstools.macros import firrtl.ir.{Circuit, NoInfo} import firrtl.passes.RemoveEmpty import firrtl.Parser.parse -import firrtl.Utils.ceilLog2 +import firrtl.Utils.getUIntWidth import java.io.{File, StringWriter} import mdf.macrolib.SRAMMacro @@ -247,10 +247,10 @@ trait HasSimpleTestGenerator { val v = s"${generatorType}${extraTagPrefixed}.v" lazy val mem_name = "target_memory" - val mem_addr_width = ceilLog2(memDepth) + val mem_addr_width = getUIntWidth(memDepth-1) lazy val lib_name = "awesome_lib_mem" - val lib_addr_width = ceilLog2(libDepth) + val lib_addr_width = getUIntWidth(libDepth-1) // Override these to change the port prefixes if needed. def libPortPrefix: String = "lib"