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Merge pull request #1823 from ucb-bar/gpiopins

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Add GPIOPunchthrough harnessbinder
This commit is contained in:
Jerry Zhao
2024-03-15 10:00:17 -07:00
committed by GitHub
parent 146efa00e9 3c67df3b44
commit 8d326e97f9
2 changed files with 9 additions and 0 deletions
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1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -20,6 +20,7 @@ class AbstractConfig extends Config(
new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */ new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */
new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */ new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */
new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */ new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */
new chipyard.harness.WithGPIOPinsTiedOff ++ /** tie-off chiptop GPIO-pins, if GPIO-punchthrough is used */
new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */ new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */
new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */ new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */
new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */ new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */

8
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -44,6 +44,14 @@ class HarnessBinder[T <: HasHarnessInstantiators, S <: Port[_]](
class WithGPIOTiedOff extends HarnessBinder({ class WithGPIOTiedOff extends HarnessBinder({
case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => { case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => {
port.io <> AnalogConst(0) port.io <> AnalogConst(0)
}
})
class WithGPIOPinsTiedOff extends HarnessBinder({
case (th: HasHarnessInstantiators, port: GPIOPinsPort, chipId: Int) => {
port.io := DontCare
} }
}) })