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[FireChip] Remove by3 clock division FASED config

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David Biancolin
2019-10-13 14:08:05 -04:00
parent abe5262ae7
commit 8c28f03ba1
1 changed files with 0 additions and 1 deletions
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generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -89,7 +89,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
// FASED Config Aliases. This to enable config generation via "_" concatenation // FASED Config Aliases. This to enable config generation via "_" concatenation
// which requires that all config classes be defined in the same package // which requires that all config classes be defined in the same package
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div
// L2 Config Aliases. For use with "_" concatenation // L2 Config Aliases. For use with "_" concatenation
class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache