From 8c28f03ba188dba9fe9c58d66469e8987349c75f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Oct 2019 14:08:05 -0400 Subject: [PATCH] [FireChip] Remove by3 clock division FASED config --- generators/firechip/src/main/scala/TargetConfigs.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 27af7548..9839c14f 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -89,7 +89,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => { // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB -class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div // L2 Config Aliases. For use with "_" concatenation class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache