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Fix spike interface

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This commit is contained in:
Jerry Zhao
2023-01-07 12:12:13 -08:00
parent 2badb7e3f6
commit 8b6a7f65dd
2 changed files with 22 additions and 10 deletions
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26
generators/chipyard/src/main/resources/csrc/spiketile.cc
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@@ -252,13 +252,24 @@ extern "C" void spike_tile(int hartid, char* isa,
dcache_ways, dcache_sets,
cacheable, uncacheable, readonly_uncacheable, executable,
icache_sourceids, dcache_sourceids);
std::string* isastr = new std::string(isa);
cfg_t* cfg = new cfg_t(std::make_pair(0, 0),
nullptr,
isastr->c_str(),
"MSU",
"vlen:128,elen:64",
false,
endianness_little,
false,
pmpregions,
std::vector<mem_cfg_t>(),
std::vector<int>(),
false);
processor_t* p = new processor_t(isa_parser,
"vlen:128,elen:64",
cfg,
simif,
hartid,
false,
endianness_little,
false,
log_file->get(),
sout);
@@ -901,10 +912,11 @@ void spike_thread_main(void* arg)
host->switch_to();
}
while (tile->max_insns != 0) {
uint64_t last_bits = tile->proc->get_last_bits();
if (insn_should_fence(last_bits) && !tile->simif->stq_empty()) {
host->switch_to();
}
// TODO: Fences don't work
// uint64_t last_bits = tile->proc->get_last_bits();
// if (insn_should_fence(last_bits) && !tile->simif->stq_empty()) {
// host->switch_to();
// }
tile->proc->step(1);
tile->max_insns--;
tile->proc->get_state()->mcycle->write(tile->simif->cycle);