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Merge pull request #1201 from sant0s12/main

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Fix DefaultClockFrequencyKey rounding
This commit is contained in:
Abraham Gonzalez
2022-09-01 10:55:55 -07:00
committed by GitHub
parent 3cd952bd32 5145b12695
commit 8a96f7c177
1 changed files with 3 additions and 3 deletions
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6
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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@@ -38,17 +38,17 @@ class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockN
fMHz) fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get.toDouble / (1000 * 1000))
}) })
class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get.toDouble / (1000 * 1000))
}) })
class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => {
case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
Seq((cName: String) => site(key).dtsFrequency.flatMap { f => Seq((cName: String) => site(key).dtsFrequency.flatMap { f =>
re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } re.findFirstIn(cName).map {_ => (f.toDouble / (1000 * 1000)) }
}) })
}) })