From 8a4fc7c82f4f5fbfedea44b2d1ee813f27d65c7e Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Tue, 2 Jan 2024 14:23:07 -0800 Subject: [PATCH] [ci skip] update docs with chip id pin --- docs/Generators/TestChipIP.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 2c382d4f..32e76f5b 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -92,3 +92,15 @@ The SPI flash model is a device that models a simple SPI flash device. It curren only supports single read, quad read, single write, and quad write instructions. The memory is backed by a file which is provided using ``+spiflash#=``, where ``#`` is the SPI flash ID (usually ``0``). + +Chip ID Pin +--------------- + +The chip ID pin sets the chip ID for the chip it is added to. This is most useful in +multi-chip configs. The pin value is driven by the chip ID value set in the harness +binder and the chip ID value can be read through MMIO at the address ``0x2000`` by default. + +The pin can be added to a system with the ``testchipip.soc.WithChipIdPin`` config. The pin +width and MMIO address are parameterizable and can be set by passing ``ChipIdPinParams`` as an +argument to the config. The width can additionally be set using the ``testchipip.soc.WithChipIdPinWidth`` +config.