diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index 10c9be23..c7c6cae2 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -48,44 +48,42 @@ class ChipLikeRocketConfig extends Config(
 class ChipBringupHostConfig extends Config(
   //=============================
   // Set up TestHarness for standalone-sim
-  // These fragments only affect the design when simulated by itself (without the ChipLikeRocketConfig)
   //=============================
-  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
-  new chipyard.harness.WithSerialTLTiedOff ++ // when doing standalone sim, tie off the serial-tl port
-  new chipyard.harness.WithSimTSIToUARTTSI ++
-  new chipyard.iobinders.WithSerialTLPunchthrough ++
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++  // Generate absolute frequencies
+  new chipyard.harness.WithSerialTLTiedOff ++                       // when doing standalone sim, tie off the serial-tl port
+  new chipyard.harness.WithSimTSIToUARTTSI ++                       // Attach SimTSI-over-UART to the UART-TSI port
+  new chipyard.iobinders.WithSerialTLPunchthrough ++                // Don't generate IOCells for the serial TL (this design maps to FPGA)
 
   //=============================
   // Setup the SerialTL side on the bringup device
   //=============================
   new testchipip.WithSerialTLWidth(4) ++                                       // match width with the chip
-  new testchipip.WithSerialTLMem(base = 0x0, size = BigInt(1) << 48,           // accessible memory of the chip
-                                 idBits = 4, isMainMemory = false) ++
+  new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L,               // accessible memory of the chip that doesn't come from the tethered host
+                                 idBits = 4, isMainMemory = false) ++          // This assumes off-chip mem starts at 0x8000_0000
   new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 50MHz clock
 
   //============================
   // Setup bus topology on the bringup system
   //============================
-  new testchipip.WithOffchipBusManager(SBUS,
-    blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4),
-    replicationBase = Some(BigInt(1) << 48)) ++
+  new testchipip.WithOffchipBusManager(SBUS,                                   // offchip bus hans off the SBUS
+    blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accesses directly through this system
   new testchipip.WithOffchipBus ++                                             // offchip bus
 
   //=============================
   // Set up memory on the bringup system
   //=============================
-  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++         // match what the chip believes
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++         // match what the chip believes the max size should be
 
   //=============================
   // Generate the TSI-over-UART side of the bringup system
   //=============================
-  new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++     // nonstandard baud rate to improve performance
+  new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++           // nonstandard baud rate to improve performance
 
   //=============================
   // Set up clocks of the bringup system
   //=============================
-  new chipyard.clocking.WithPassthroughClockGenerator ++  // pass all the clocks through, since this isn't a chip
-  new chipyard.config.WithFrontBusFrequency(75.0) ++
+  new chipyard.clocking.WithPassthroughClockGenerator ++ // pass all the clocks through, since this isn't a chip
+  new chipyard.config.WithFrontBusFrequency(75.0) ++     // run all buses of this system at 75 MHz
   new chipyard.config.WithMemoryBusFrequency(75.0) ++
   new chipyard.config.WithPeripheryBusFrequency(75.0) ++
 
@@ -93,7 +91,7 @@ class ChipBringupHostConfig extends Config(
   new chipyard.NoCoresConfig)
 
 class TetheredChipLikeRocketConfig extends Config(
-  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute freqs for sims in the harness
-  new chipyard.harness.WithMultiChipSerialTL(0, 1) ++
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++   // use absolute freqs for sims in the harness
+  new chipyard.harness.WithMultiChipSerialTL(0, 1) ++                // connect the serial-tl ports of the chips together
   new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++
   new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))