From 89090f6b909880e1218916e5351ee20d2836533f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 15 Feb 2023 10:17:08 -0800 Subject: [PATCH] Remove need for separate SpikeCosimResources --- .../src/main/resources/vsrc/cospike.v | 70 +++++++++---------- .../chipyard/src/main/scala/Cospike.scala | 28 ++++---- .../src/main/scala/HarnessBinders.scala | 17 ++--- 3 files changed, 54 insertions(+), 61 deletions(-) diff --git a/generators/chipyard/src/main/resources/vsrc/cospike.v b/generators/chipyard/src/main/resources/vsrc/cospike.v index 0b70d365..f9d2322c 100644 --- a/generators/chipyard/src/main/resources/vsrc/cospike.v +++ b/generators/chipyard/src/main/resources/vsrc/cospike.v @@ -20,46 +20,42 @@ import "DPI-C" function void cospike_cosim(input longint cycle, ); -module CospikeResources #( - parameter ISA, - parameter PMPREGIONS, - parameter MEM0_BASE, - parameter MEM0_SIZE, - parameter NHARTS, - parameter BOOTROM) - (); +module SpikeCosim #( + parameter ISA, + parameter PMPREGIONS, + parameter MEM0_BASE, + parameter MEM0_SIZE, + parameter NHARTS, + parameter BOOTROM) ( + input clock, + input reset, + + input [63:0] cycle, + + input [63:0] hartid, + + input trace_0_valid, + input [63:0] trace_0_iaddr, + input [31:0] trace_0_insn, + input trace_0_exception, + input trace_0_interrupt, + input [63:0] trace_0_cause, + input trace_0_has_wdata, + input [63:0] trace_0_wdata, + + input trace_1_valid, + input [63:0] trace_1_iaddr, + input [31:0] trace_1_insn, + input trace_1_exception, + input trace_1_interrupt, + input [63:0] trace_1_cause, + input trace_1_has_wdata, + input [63:0] trace_1_wdata + ); + initial begin cospike_set_sysinfo(ISA, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM); end; -endmodule; // CospikeResources - - -module SpikeCosim ( - input clock, - input reset, - - input [63:0] cycle, - - input [63:0] hartid, - - input trace_0_valid, - input [63:0] trace_0_iaddr, - input [31:0] trace_0_insn, - input trace_0_exception, - input trace_0_interrupt, - input [63:0] trace_0_cause, - input trace_0_has_wdata, - input [63:0] trace_0_wdata, - - input trace_1_valid, - input [63:0] trace_1_iaddr, - input [31:0] trace_1_insn, - input trace_1_exception, - input trace_1_interrupt, - input [63:0] trace_1_cause, - input trace_1_has_wdata, - input [63:0] trace_1_wdata - ); always @(posedge clock) begin if (!reset) begin diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index 14eb018d..7b663b24 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -12,27 +12,23 @@ import freechips.rocketchip.util._ import testchipip.TileTraceIO -class CospikeResources( +case class SpikeCosimConfig( isa: String, pmpregions: Int, mem0_base: BigInt, mem0_size: BigInt, nharts: Int, bootrom: String -) extends BlackBox(Map( - "ISA" -> StringParam(isa), - "PMPREGIONS" -> IntParam(pmpregions), - "MEM0_BASE" -> IntParam(mem0_base), - "MEM0_SIZE" -> IntParam(mem0_size), - "NHARTS" -> IntParam(nharts), - "BOOTROM" -> StringParam(bootrom) -)) with HasBlackBoxResource { - val io = IO(new Bundle {}) - addResource("/csrc/cospike.cc") - addResource("/vsrc/cospike.v") -} +) -class SpikeCosim extends BlackBox with HasBlackBoxResource +class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( + "ISA" -> StringParam(cfg.isa), + "PMPREGIONS" -> IntParam(cfg.pmpregions), + "MEM0_BASE" -> IntParam(cfg.mem0_base), + "MEM0_SIZE" -> IntParam(cfg.mem0_size), + "NHARTS" -> IntParam(cfg.nharts), + "BOOTROM" -> StringParam(cfg.bootrom) +)) with HasBlackBoxResource { addResource("/csrc/cospike.cc") addResource("/vsrc/cospike.v") @@ -56,8 +52,8 @@ class SpikeCosim extends BlackBox with HasBlackBoxResource object SpikeCosim { - def apply(trace: TileTraceIO, hartid: Int) = { - val cosim = Module(new SpikeCosim) + def apply(trace: TileTraceIO, hartid: Int, cfg: SpikeCosimConfig) = { + val cosim = Module(new SpikeCosim(cfg)) val cycle = withClockAndReset(trace.clock, trace.reset) { val r = RegInit(0.U(64.W)) r := r + 1.U diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index f8e94044..a47b08e0 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -338,14 +338,15 @@ class WithCospike extends ComposeHarnessBinder({ implicit val p = chipyard.iobinders.GetSystemParameters(system) val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem] val tiles = chipyardSystem.tiles - val isa = tiles.headOption.map(_.isaDTS).getOrElse("") - val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)) - val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)) - val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0) - val nharts = tiles.size - val bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") - val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom)) - ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2)) } + val cfg = SpikeCosimConfig( + isa = tiles.headOption.map(_.isaDTS).getOrElse(""), + mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)), + mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), + pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0), + nharts = tiles.size, + bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") + ) + ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) } } })