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- fix call to ceilLog2 in macros

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chick
2020-09-29 10:59:48 -07:00
parent 1a82c082b3
commit 8903c04c2d
1 changed files with 2 additions and 2 deletions
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4
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -248,10 +248,10 @@ trait HasSimpleTestGenerator {
val v = s"${generatorType}${extraTagPrefixed}.v" val v = s"${generatorType}${extraTagPrefixed}.v"
lazy val mem_name = "target_memory" lazy val mem_name = "target_memory"
val mem_addr_width = ceilLog2(memDepth) val mem_addr_width = MacroCompilerMath.ceilLog2(memDepth)
lazy val lib_name = "awesome_lib_mem" lazy val lib_name = "awesome_lib_mem"
val lib_addr_width = ceilLog2(libDepth) val lib_addr_width = MacroCompilerMath.ceilLog2(libDepth)
// Override these to change the port prefixes if needed. // Override these to change the port prefixes if needed.
def libPortPrefix: String = "lib" def libPortPrefix: String = "lib"