Switch to UARTTSIIO

generators/chipyard/src/main/scala/IOBinders.scala

@@ -414,9 +414,9 @@ class WithCustomBootPin extends OverrideIOBinder({
 class WithUARTTSIPunchthrough extends OverrideIOBinder({
   (system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p =>
     val sys = system.asInstanceOf[BaseSubsystem]
-    val port = IO(new UARTPortIO(p.c))
-    port <> p
-    (Seq(port), Nil)
+    val uart_tsi = IO(new UARTTSIIO(p.uartParams))
+    uart_tsi <> p
+    (Seq(uart_tsi), Nil)
   }).getOrElse((Nil, Nil))
 })
 

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -318,14 +318,16 @@ class WithSimTSIOverSerialTL extends OverrideHarnessBinder({
 })
 
 class WithSimUARTToUARTTSI extends OverrideHarnessBinder({
-  (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
+  (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
-    ports.map({ port =>
-      UARTAdapter.connect(Seq(port),
-        baudrate=port.c.initBaudRate,
+    require(ports.size <= 1)
+    ports.map { port => {
+      UARTAdapter.connect(Seq(port.uart),
+        baudrate=port.uartParams.initBaudRate,
         clockFrequency=th.getHarnessBinderClockFreqHz.toInt,
         forcePty=true)
-    })
+      assert(!port.dropped)
+    }}
   }
 })