All depth tests now fully automatic
This commit is contained in:
Edward Wang
@@ -336,66 +336,6 @@ class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGene
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//execute(mem, lib, false, output)
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}
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//~ class SplitDepth2048x8_r_mw extends MacroCompilerSpec {
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//~ val mem = new File(macroDir, "mem-2048x8-r-mw.json")
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//~ val lib = new File(macroDir, "lib-1024x8-r-mw.json")
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//~ val v = new File(testDir, "split_depth_2048x8_r_mw.v")
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//~ val output =
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//~ """
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//~ circuit name_of_sram_module :
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//~ module name_of_sram_module :
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//~ input clock : Clock
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//~ input W0A : UInt<11>
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//~ input W0I : UInt<8>
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//~ input W0E : UInt<1>
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//~ input W0M : UInt<1>
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//~ input clock : Clock
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//~ input R0A : UInt<11>
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//~ output R0O : UInt<8>
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//~ node W0A_sel = bits(W0A, 10, 10)
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//~ node R0A_sel = bits(R0A, 10, 10)
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//~ inst mem_0_0 of vendor_sram
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//~ mem_0_0.clock <= clock
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//~ mem_0_0.W0A <= W0A
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//~ mem_0_0.W0I <= bits(W0I, 7, 0)
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//~ mem_0_0.W0M <= bits(W0M, 0, 0)
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//~ mem_0_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h0")))
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//~ mem_0_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h0")))
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//~ mem_0_0.clock <= clock
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//~ mem_0_0.R0A <= R0A
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//~ node R0O_0_0 = bits(mem_0_0.R0O, 7, 0)
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//~ node R0O_0 = R0O_0_0
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//~ inst mem_1_0 of vendor_sram
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//~ mem_1_0.clock <= clock
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//~ mem_1_0.W0A <= W0A
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//~ mem_1_0.W0I <= bits(W0I, 7, 0)
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//~ mem_1_0.W0M <= bits(W0M, 0, 0)
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//~ mem_1_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h1")))
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//~ mem_1_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h1")))
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//~ mem_1_0.clock <= clock
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//~ mem_1_0.R0A <= R0A
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//~ node R0O_1_0 = bits(mem_1_0.R0O, 7, 0)
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//~ node R0O_1 = R0O_1_0
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//~ R0O <= mux(eq(R0A_sel, UInt<1>("h0")), R0O_0, mux(eq(R0A_sel, UInt<1>("h1")), R0O_1, UInt<1>("h0")))
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//~ extmodule vendor_sram :
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//~ input clock : Clock
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//~ input R0A : UInt<10>
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//~ output R0O : UInt<8>
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//~ input clock : Clock
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//~ input W0A : UInt<10>
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//~ input W0I : UInt<8>
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//~ input W0E : UInt<1>
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//~ input W0W : UInt<1>
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//~ input W0M : UInt<1>
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//~ defname = vendor_sram
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//~ """
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//~ compile(mem, lib, v, false)
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//~ execute(mem, lib, false, output)
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//~ }
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// Try an extra port
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class SplitDepth2048x8_extraPort extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
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import mdf.macrolib._
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@@ -453,3 +393,132 @@ circuit target_memory :
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compile(mem, lib, v, false)
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execute(mem, lib, false, outputCustom)
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}
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// Split read and (masked) write ports (r+w).
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class SplitDepth_SplitPorts extends MacroCompilerSpec with HasSRAMGenerator {
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lazy val width = 8
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lazy val mem_depth = 2048
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lazy val lib_depth = 1024
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override val memPrefix = testDir
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override val libPrefix = testDir
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import mdf.macrolib._
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"Non-masked split lib; split mem" should "split fine" in {
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val lib = "lib-split_depth-r-mw-lib-regular-mem.json"
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val mem = "mem-split_depth-r-mw-lib-regular-mem.json"
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val v = "split_depth-r-mw-lib-regular-mem.v"
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val libMacro = SRAMMacro(
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macroType=SRAM,
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name="awesome_lib_mem",
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width=width,
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depth=lib_depth,
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family="1r1w",
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ports=Seq(
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generateReadPort("innerA", width, lib_depth),
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generateWritePort("innerB", width, lib_depth)
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)
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)
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val memMacro = SRAMMacro(
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macroType=SRAM,
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name="target_memory",
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width=width,
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depth=mem_depth,
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family="1r1w",
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ports=Seq(
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generateReadPort("outerB", width, mem_depth),
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generateWritePort("outerA", width, mem_depth)
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)
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)
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writeToLib(mem, Seq(memMacro))
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writeToLib(lib, Seq(libMacro))
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val output =
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"""
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circuit target_memory :
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module target_memory :
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input outerB_clk : Clock
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input outerB_addr : UInt<11>
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output outerB_dout : UInt<8>
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input outerA_clk : Clock
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input outerA_addr : UInt<11>
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input outerA_din : UInt<8>
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input outerA_write_en : UInt<1>
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node outerB_addr_sel = bits(outerB_addr, 10, 10)
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node outerA_addr_sel = bits(outerA_addr, 10, 10)
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inst mem_0_0 of awesome_lib_mem
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mem_0_0.innerA_clk <= outerB_clk
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mem_0_0.innerA_addr <= outerB_addr
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node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
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node outerB_dout_0 = outerB_dout_0_0
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mem_0_0.innerB_clk <= outerA_clk
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mem_0_0.innerB_addr <= outerA_addr
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mem_0_0.innerB_din <= bits(outerA_din, 7, 0)
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mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0")))
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inst mem_1_0 of awesome_lib_mem
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mem_1_0.innerA_clk <= outerB_clk
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mem_1_0.innerA_addr <= outerB_addr
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node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
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node outerB_dout_1 = outerB_dout_1_0
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mem_1_0.innerB_clk <= outerA_clk
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mem_1_0.innerB_addr <= outerA_addr
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mem_1_0.innerB_din <= bits(outerA_din, 7, 0)
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mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1")))
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outerB_dout <= mux(eq(outerB_addr_sel, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
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extmodule awesome_lib_mem :
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input innerA_clk : Clock
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input innerA_addr : UInt<10>
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output innerA_dout : UInt<8>
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input innerB_clk : Clock
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input innerB_addr : UInt<10>
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input innerB_din : UInt<8>
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input innerB_write_en : UInt<1>
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defname = awesome_lib_mem
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"""
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compile(mem, lib, v, false)
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execute(mem, lib, false, output)
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}
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"Non-masked split lib; regular mem" should "split fine" in {
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// Enable this test when the memory compiler can compile non-matched
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// memories (e.g. mrw mem and r+mw lib).
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// Right now all we can get is a "port count must match" error.
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// [edwardw]: does this even make sense? Can we compile a 2-ported memory using 1-ported memories?
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pending
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val lib = "lib-split_depth-r-mw-lib-regular-mem.json"
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val mem = "mem-split_depth-r-mw-lib-regular-mem.json"
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val v = "split_depth-r-mw-lib-regular-mem.v"
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val libMacro = SRAMMacro(
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macroType=SRAM,
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name="awesome_lib_mem",
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width=width,
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depth=lib_depth,
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family="1rw",
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ports=Seq(
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generateReadPort("innerA", width, lib_depth),
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generateWritePort("innerB", width, lib_depth)
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)
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)
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writeToLib(mem, Seq(generateSRAM("target_memory", "outer", width, mem_depth)))
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writeToLib(lib, Seq(libMacro))
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val output =
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"""
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TODO
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"""
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compile(mem, lib, v, false)
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execute(mem, lib, false, output)
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}
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}
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