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Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

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* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
This commit is contained in:
Colin Schmidt
2019-12-12 13:39:09 -08:00
committed by David Biancolin
parent c0564d319b
commit 86a473dbf6
22 changed files with 36 additions and 33 deletions
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2
generators/tracegen/src/main/scala/TestHarness.scala
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@@ -17,7 +17,7 @@ class TestHarness(implicit p: Parameters) extends Module {
object Generator extends GeneratorApp {
// specify the name that the generator outputs files as
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
// generate files
generateFirrtl