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Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

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* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
This commit is contained in:
Colin Schmidt
2019-12-12 13:39:09 -08:00
committed by David Biancolin
parent c0564d319b
commit 86a473dbf6
22 changed files with 36 additions and 33 deletions
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4
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.debug.DebugModuleParams
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import boom.common.BoomTilesKey
import testchipip.{BlockDeviceKey, BlockDeviceConfig}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -77,7 +77,7 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
// Disables clock-gating; doesn't play nice with our FAME-1 pass
class WithoutClockGating extends Config((site, here, up) => {
case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false)
case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
})
// Testing configurations