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Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

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* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
This commit is contained in:
Colin Schmidt
2019-12-12 13:39:09 -08:00
committed by David Biancolin
parent c0564d319b
commit 86a473dbf6
22 changed files with 36 additions and 33 deletions
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2
generators/example/src/main/scala/Generator.scala
View File

@@ -31,7 +31,7 @@ object Generator extends GeneratorApp {
}
// specify the name that the generator outputs files as
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
// generate files
generateFirrtl

6
generators/example/src/main/scala/TestHarness.scala
View File

@@ -30,7 +30,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
val dut = p(BuildTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.debug.foreach(_ := DontCare)
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()
dut.dontTouchPorts()
@@ -65,7 +65,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
dut.reset := reset.asBool | dut.debug.ndreset
dut.reset := reset.asBool | dut.debug.get.ndreset
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()
dut.dontTouchPorts()
@@ -83,5 +83,5 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
}
})
Debug.connectDebug(dut.debug, clock, reset.asBool, io.success)
Debug.connectDebug(dut.debug, dut.psd, clock, reset.asBool, io.success)
}