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[firechip] Make some TracerV tests less strict

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This commit is contained in:
David Biancolin
2019-09-26 20:49:50 +00:00
parent 4c45d2e48a
commit 868c2b3b6d
2 changed files with 4 additions and 3 deletions
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4
generators/firechip/src/test/scala/ScalaTestSuite.scala
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@@ -109,10 +109,10 @@ abstract class FireSimTestSuite(
val lines = Source.fromFile(file).getLines.toList
lines.filter(_.startsWith("TRACEPORT")).drop(dropLines)
}
val resetLength = 50
val resetLength = 51
val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"))
val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length")
assert(verilatedOutput.nonEmpty)
for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
assert(vPrint == sPrint)