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Use EICG_wrapper model as addResource/Path | Fix Makefile parsing

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abejgonzalez
2023-02-15 14:19:55 -08:00
parent 660c63fb34
commit 85fe061244
4 changed files with 2 additions and 8 deletions
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3
fpga/Makefile
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@@ -90,9 +90,6 @@ fpga_common_script_dir := $(fpga_dir)/common/tcl
######################################################################################### #########################################################################################
# setup misc. sim files # setup misc. sim files
######################################################################################### #########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
# copy files but ignore *.h files in *.f (match vcs) # copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) $(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(OUT_DIR) cp -f $^ $(OUT_DIR)

1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -51,6 +51,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)

3
sims/common-sim-flags.mk
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@@ -33,6 +33,3 @@ SIM_LDFLAGS = \
-lfesvr \ -lfesvr \
-ldramsim \ -ldramsim \
$(EXTRA_SIM_LDFLAGS) $(EXTRA_SIM_LDFLAGS)
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

3
vlsi/Makefile
View File

@@ -54,7 +54,7 @@ endif
######################################################################################### #########################################################################################
# general rules # general rules
######################################################################################### #########################################################################################
.PHONY: default .PHONY: default all
default: all default: all
all: drc lvs all: drc lvs
@@ -82,7 +82,6 @@ ifneq ($(CUSTOM_VLOG), )
else else
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL) cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
endif endif
######################################################################################### #########################################################################################