Add ARTY100t bringup + TSI-over-UART

2023-02-12 21:31:29 -08:00
parent 3dc4fff29b
commit 85fa9d1120
18 changed files with 240 additions and 33 deletions
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -37,6 +37,10 @@ class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
 })

+class WithNoUART extends Config((site, here, up) => {
+  case PeripheryUARTKey => Nil
+})
+
 class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
  case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
 })