Add ARTY100t bringup + TSI-over-UART

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -321,6 +321,24 @@ class WithSimSerial extends OverrideHarnessBinder({
   }
 })
 
+class WithUARTSerial extends OverrideHarnessBinder({
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    ports.map({ port =>
+      val freq = p(PeripheryBusKey).dtsFrequency.get
+      val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
+      withClockAndReset(th.buildtopClock, th.buildtopReset) {
+        val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
+        val uart_to_tsi = Module(new UARTToTSI(freq))
+        UARTAdapter.connect(Seq(uart_to_tsi.io.uart), uart_to_tsi.div)
+        ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial)
+        th.success := false.B
+      }
+    })
+  }
+})
+
+
 class WithTraceGenSuccess extends OverrideHarnessBinder({
   (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => {
     ports.map { p => when (p) { th.success := true.B } }

generators/chipyard/src/main/scala/IOBinders.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode
 import freechips.rocketchip.util._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
+import freechips.rocketchip.tilelink.{TLBundle}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -23,6 +24,7 @@ import barstools.iocell.chisel._
 
 import testchipip._
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
+import chipyard.{CanHaveMasterTLMemPort}
 import chipyard.clocking.{HasChipyardPRCI, DividerOnlyClockGenerator}
 
 import scala.reflect.{ClassTag}
@@ -381,6 +383,15 @@ class WithCustomBootPin extends OverrideIOBinder({
   }).getOrElse((Nil, Nil))
 })
 
+class WithTLMemPunchthrough extends OverrideIOBinder({
+  (system: CanHaveMasterTLMemPort) => {
+    val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
+    io_tl_mem_pins_temp <> system.mem_tl
+    (Seq(io_tl_mem_pins_temp), Nil)
+  }
+})
+
+
 class WithDontTouchPorts extends OverrideIOBinder({
   (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
 })

generators/chipyard/src/main/scala/TestHarness.scala

@@ -27,7 +27,6 @@ trait HasHarnessSignalReferences {
   def getRefClockFreq: Double = refClockFreq
   def buildtopClock: Clock
   def buildtopReset: Reset
-  def dutReset: Reset
   def success: Bool
 }
 
@@ -91,7 +90,6 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
 
   io.success := false.B
 
-  val dutReset = buildtopReset.asAsyncReset
   val success = io.success
 
   lazyDut match { case d: HasIOBinders =>

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -28,6 +28,7 @@ class AbstractConfig extends Config(
   // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through
   new chipyard.iobinders.WithAXI4MemPunchthrough ++
   new chipyard.iobinders.WithAXI4MMIOPunchthrough ++
+  new chipyard.iobinders.WithTLMemPunchthrough ++
   new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
   new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
   new chipyard.iobinders.WithNICIOPunchthrough ++

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -21,6 +21,14 @@ class TinyRocketConfig extends Config(
   new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
   new chipyard.config.AbstractConfig)
 
+class UARTTSIRocketConfig extends Config(
+  new chipyard.harness.WithUARTSerial ++
+  new chipyard.config.WithNoUART ++
+  new chipyard.config.WithMemoryBusFrequency(10) ++              
+  new chipyard.config.WithPeripheryBusFrequency(10) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new chipyard.config.AbstractConfig)
+
 class SimAXIRocketConfig extends Config(
   new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -37,6 +37,10 @@ class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
     UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
 })
 
+class WithNoUART extends Config((site, here, up) => {
+  case PeripheryUARTKey => Nil
+})
+
 class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
   case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
 })

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -2,6 +2,7 @@ package chipyard.config
 
 import freechips.rocketchip.config.{Config}
 import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
+import freechips.rocketchip.diplomacy.{DTSTimebase}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence
 class WithBroadcastManager extends Config((site, here, up) => {
@@ -11,3 +12,7 @@ class WithBroadcastManager extends Config((site, here, up) => {
 class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
 })
+
+class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
+  case DTSTimebase => freqMHz
+})