Add ARTY100t bringup + TSI-over-UART

2023-02-12 21:31:29 -08:00
parent 3dc4fff29b
commit 85fa9d1120
18 changed files with 240 additions and 33 deletions
--- a/fpga/src/main/scala/vcu118/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/IOBinders.scala
@@ -42,11 +42,3 @@ class WithSPIIOPassthrough  extends OverrideLazyIOBinder({
    }
  }
 })
-
-class WithTLIOPassthrough extends OverrideIOBinder({
-  (system: CanHaveMasterTLMemPort) => {
-    val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
-    io_tl_mem_pins_temp <> system.mem_tl
-    (Seq(io_tl_mem_pins_temp), Nil)
-  }
-})