Add ARTY100t bringup + TSI-over-UART

fpga/src/main/scala/arty/Configs.scala

@@ -15,30 +15,20 @@ import testchipip.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
-class WithDefaultPeripherals extends Config((site, here, up) => {
-  case PeripheryUARTKey => List(
-    UARTParams(address = 0x10013000))
-  case DTSTimebase => BigInt(32768)
-  case JtagDTMKey => new JtagDTMConfig (
-    idcodeVersion = 2,
-    idcodePartNum = 0x000,
-    idcodeManufId = 0x489,
-    debugIdleCycles = 5)
-  case SerialTLKey => None // remove serialized tl port
-})
-
 // DOC include start: AbstractArty and Rocket
 class WithArtyTweaks extends Config(
   new WithArtyJTAGHarnessBinder ++
   new WithArtyUARTHarnessBinder ++
   new WithArtyResetHarnessBinder ++
   new WithDebugResetPassthrough ++
-  new WithDefaultPeripherals ++
-  new freechips.rocketchip.subsystem.WithNBreakpoints(2)
+
+  new chipyard.config.WithDTSTimebase(32768) ++
+  new testchipip.WithNoSerialTL
 )
 
 class TinyRocketArtyConfig extends Config(
   new WithArtyTweaks ++
+  new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
   new chipyard.TinyRocketConfig
 )
 // DOC include end: AbstractArty and Rocket

fpga/src/main/scala/arty100t/Configs.scala

@@ -0,0 +1,40 @@
+// See LICENSE for license details.
+package chipyard.fpga.arty100t
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.uart._
+import sifive.fpgashells.shell.{DesignKey}
+
+import testchipip.{SerialTLKey}
+
+import chipyard.{BuildSystem}
+
+// don't use FPGAShell's DesignKey
+class WithNoDesignKey extends Config((site, here, up) => {
+  case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+})
+
+class WithArty100TTweaks extends Config(
+  new WithArty100TUARTTSI ++
+  new WithArty100TDDRTL ++
+  new WithNoDesignKey ++
+  new chipyard.config.WithNoDebug ++ // no jtag
+  new chipyard.config.WithNoUART ++
+  new chipyard.config.WithTLBackingMemory ++
+  new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) // 256mb on ARTY
+)
+
+class RocketArtyConfig extends Config(
+  new WithArty100TTweaks ++
+  new chipyard.config.WithMemoryBusFrequency(10.0) ++  // 2x the U540 freq (appropriate for a 128b Mbus)
+  new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
+  new chipyard.config.WithBroadcastManager ++ // no l2
+  new chipyard.RocketConfig
+)

fpga/src/main/scala/arty100t/Harness.scala

@@ -0,0 +1,58 @@
+package chipyard.fpga.arty100t
+
+import chisel3._
+
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.tilelink.{TLClientNode}
+
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.shell._
+import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
+
+import sifive.blocks.devices.uart._
+
+import chipyard._
+import chipyard.harness.{ApplyHarnessBinders}
+import chipyard.iobinders.{HasIOBinders}
+
+class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences
+{
+  def dp = designParameters
+
+  val chiptop = LazyModule(p(BuildTop)(p))
+
+  val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
+  val harnessSysPLL = dp(PLLFactoryKey)()
+  println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
+  val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
+  val dutWrangler = LazyModule(new ResetWrangler)
+  val dutGroup = ClockGroup()
+  dutClock := dutWrangler.node := dutGroup := harnessSysPLL
+
+  harnessSysPLL := clockOverlay.overlayOutput.node
+
+  val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
+  val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
+
+  val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL))
+  val ddrInParams = chiptop match { case td: ChipTop =>
+    td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
+      lsys.memTLNode.edges.in(0)
+    }
+  }
+  val ddrClient = TLClientNode(Seq(ddrInParams.master))
+  ddrOverlay.overlayOutput.ddr := ddrClient
+
+  def buildtopClock = dutClock.in.head._1.clock
+  def buildtopReset = dutClock.in.head._1.reset
+  def success = { require(false, "Unused"); false.B }
+
+  InModuleBody {
+    chiptop match { case d: HasIOBinders =>
+      ApplyHarnessBinders(this, d.lazySystem, d.portMap)
+    }
+  }
+
+}

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -0,0 +1,48 @@
+package chipyard.fpga.arty100t
+
+import chisel3._
+
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.jtag.{JTAGIO}
+import freechips.rocketchip.subsystem.{PeripheryBusKey}
+import freechips.rocketchip.tilelink.{TLBundle}
+import freechips.rocketchip.util.{HeterogeneousBag}
+
+import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
+import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
+import sifive.blocks.devices.pinctrl.{BasePin}
+
+import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
+
+import chipyard._
+import chipyard.harness._
+import chipyard.iobinders.JTAGChipIO
+
+import testchipip._
+
+class WithArty100TUARTTSI extends OverrideHarnessBinder({
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    ports.map({ port =>
+      val freq = p(PeripheryBusKey).dtsFrequency.get
+      val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
+      withClockAndReset(th.buildtopClock, th.buildtopReset) {
+        val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
+        val uart_to_tsi = Module(new UARTToTSI(freq))
+        ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial)
+        th.asInstanceOf[Arty100THarness].io_uart_bb.bundle <> uart_to_tsi.io.uart
+      }
+    })
+  }
+})
+
+class WithArty100TDDRTL extends OverrideHarnessBinder({
+  (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
+    require(ports.size == 1)
+    val artyTh = th.asInstanceOf[Arty100THarness]
+    val bundles = artyTh.ddrClient.out.map(_._1)
+    val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+    bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+    ddrClientBundle <> ports.head
+  }
+})

fpga/src/main/scala/arty100t/IOBinders.scala

@@ -0,0 +1,23 @@
+package chipyard.fpga.arty100t
+
+import chisel3._
+import chisel3.experimental.{IO}
+
+import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
+
+import chipyard.iobinders.{ComposeIOBinder}
+
+// class WithDebugResetPassthrough extends ComposeIOBinder({
+//   (system: HasPeripheryDebugModuleImp) => {
+//     // Debug module reset
+//     val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
+//     io_ndreset := system.debug.get.ndreset
+
+//     // JTAG reset
+//     val sjtag = system.debug.get.systemjtag.get
+//     val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
+//     sjtag.reset := io_sjtag_reset
+
+//     (Seq(io_ndreset, io_sjtag_reset), Nil)
+//   }
+// })

fpga/src/main/scala/vcu118/Configs.scala

@@ -47,7 +47,6 @@ class WithVCU118Tweaks extends Config(
   // io binders
   new WithUARTIOPassthrough ++
   new WithSPIIOPassthrough ++
-  new WithTLIOPassthrough ++
   // other configuration
   new WithDefaultPeripherals ++
   new chipyard.config.WithTLBackingMemory ++ // use TL backing memory

fpga/src/main/scala/vcu118/IOBinders.scala

@@ -42,11 +42,3 @@ class WithSPIIOPassthrough  extends OverrideLazyIOBinder({
     }
   }
 })
-
-class WithTLIOPassthrough extends OverrideIOBinder({
-  (system: CanHaveMasterTLMemPort) => {
-    val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
-    io_tl_mem_pins_temp <> system.mem_tl
-    (Seq(io_tl_mem_pins_temp), Nil)
-  }
-})

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -7,15 +7,15 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridg
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
-import sifive.fpgashells.shell.xilinx.{VCU118ShellBasicOverlays, UARTVCU118ShellPlacer, SDIOVCU118ShellPlacer, JTAGDebugBScanVCU118ShellPlacer, JTAGDebugVCU118ShellPlacer, cJTAGDebugVCU118ShellPlacer, PCIeVCU118FMCShellPlacer, PCIeVCU118EdgeShellPlacer, VCU118ShellPMOD, ChipLinkVCU118PlacedOverlay}
+import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
-import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, ClockInputShellInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, SPIOverlayKey, SPIDesignInput, SPIShellInput, JTAGDebugOverlayKey, JTAGDebugShellInput, JTAGDebugBScanOverlayKey, JTAGDebugBScanShellInput, cJTAGDebugOverlayKey, cJTAGDebugShellInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, DDRShellInput}
+import sifive.fpgashells.shell._
 import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
 
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
 
-import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey}
+import chipyard._
 import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness.{ApplyHarnessBinders}