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Add ARTY100t bringup + TSI-over-UART

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This commit is contained in:
Jerry Zhao
2023-02-12 21:31:29 -08:00
parent 3dc4fff29b
commit 85fa9d1120
18 changed files with 240 additions and 33 deletions
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18
fpga/Makefile
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@@ -57,7 +57,6 @@ ifeq ($(SUB_PROJECT),bringup)
BOARD ?= vcu118
FPGA_BRAND ?= xilinx
endif
ifeq ($(SUB_PROJECT),arty)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
@@ -72,6 +71,20 @@ ifeq ($(SUB_PROJECT),arty)
BOARD ?= arty
FPGA_BRAND ?= xilinx
endif
ifeq ($(SUB_PROJECT),arty100t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
MODEL ?= Arty100THarness
VLOG_MODEL ?= Arty100THarness
MODEL_PACKAGE ?= chipyard.fpga.arty100t
CONFIG ?= RocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty100t
GENERATOR_PACKAGE ?= chipyard
TB ?= none # unused
TOP ?= ChipTop
BOARD ?= arty_a7_100
FPGA_BRAND ?= xilinx
endif
include $(base_dir)/variables.mk
@@ -111,8 +124,7 @@ include $(base_dir)/common.mk
# copy from other directory
#########################################################################################
all_vsrcs := \
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
#########################################################################################
# vivado rules