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This commit is contained in:
Edward Wang
2017-07-31 15:53:46 -07:00
committed by edwardcwang
parent 519ffef50a
commit 85d18b736e
1 changed files with 2 additions and 0 deletions
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2
macros/src/main/scala/MacroCompiler.scala
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@@ -448,6 +448,8 @@ object MacroCompiler extends App {
val verilogWriter = new FileWriter(new File(params.get(Verilog).get)) val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
if (macros.nonEmpty) { if (macros.nonEmpty) {
// Note: the last macro in the input list is (seemingly arbitrarily)
// determined as the firrtl "top-level module".
val circuit = Circuit(NoInfo, macros, macros.last.name) val circuit = Circuit(NoInfo, macros, macros.last.name)
val annotations = AnnotationMap(Seq(MacroCompilerAnnotation( val annotations = AnnotationMap(Seq(MacroCompilerAnnotation(
circuit.main, params.get(Macros).get, params.get(Library), synflops))) circuit.main, params.get(Macros).get, params.get(Library), synflops)))