Remove CheckForUnsupportedFirtoolTypes
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@@ -1,72 +0,0 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.annotations.{ModuleTarget, ReferenceTarget, SingleTargetAnnotation}
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import firrtl.ir._
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import firrtl.options.Dependency
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import firrtl.passes.memlib.ReplSeqMem
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import firrtl.stage.Forms
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import firrtl.stage.{RunFirrtlTransformAnnotation}
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import firrtl.stage.TransformManager.TransformDependency
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class CheckForUnsupportedFirtoolTypes extends Transform with DependencyAPIMigration {
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override def prerequisites: Seq[TransformDependency] = Forms.ChirrtlForm
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override def optionalPrerequisites: Seq[TransformDependency] = Seq.empty
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override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq.empty
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override def invalidates(a: Transform): Boolean = false
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def run(state: CircuitState): Boolean = {
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val c = state.circuit
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//def checkFixed(t: Type): Unit = {
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// println(s"checkFixed -> $t")
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// t match {
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// case FixedType(_, _) => {
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// runLowering = true
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// println(s"runLowering is $runLowering")
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// }
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// case _ => Unit
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// }
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//}
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def onStmtType(s: Statement): Boolean = {
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var runLowering = false
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println(s"Entering onStmtType")
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def recursive(s: Statement): Unit = {
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s match {
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case x: DefRegister => x.foreachType(_ => println(s"It works!"))
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case x: DefWire => x.foreachType(_ => println(s"1 It works!"))
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case x: DefNode => x.foreachType(_ => println(s"2 It works!"))
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case x: DefMemory => x.foreachType(_ => println(s"3 It works!"))
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case x: WDefInstance => x.foreachType(_ => println(s"4 It works!"))
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case x: Connect => x.foreachType(_ => println(s"5 It works!"))
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case x: PartialConnect => x.foreachType(_ => println(s"6 It works!"))
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case x: Block => x.foreachStmt(recursive)
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case x => x.foreachType(_ => println(s"Uh oh"))
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}
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}
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//s.foreachType(checkFixed)
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s.foreachType(_ => println("Reached"))
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runLowering
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}
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val runLoweringOverall = c.modules.map {
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case m: ExtModule => false
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case m: Module => onStmtType(m.body)
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}
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runLoweringOverall.reduce(_ || _)
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}
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def execute(state: CircuitState): CircuitState = {
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val runLoweringAnnos = Seq(RunFirrtlTransformAnnotation(new MiddleFirrtlEmitter))
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val doLowering = run(state)
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println(s"DEBUG: Final doLowering -> $doLowering")
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state.copy(annotations = state.annotations)
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}
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}
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@@ -45,9 +45,8 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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// Top Generation
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def executeTop(): Unit = {
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val annos = new FirrtlStage().execute(Array.empty, annotations) //++ Seq(
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// RunFirrtlTransformAnnotation(Dependency[CheckForUnsupportedFirtoolTypes]
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//)))
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val annos = new FirrtlStage().execute(Array.empty, annotations)
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annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
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case Some(circuit) =>
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dump(circuit, annos)
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