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[skip ci] add power-rtl and power-syn targets

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This commit is contained in:
Harrison Liew
2023-02-09 13:01:08 -08:00
parent ea65d93c8e
commit 83764d3329
5 changed files with 199 additions and 136 deletions
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137
vlsi/Makefile
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@@ -109,122 +109,6 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
cd $(vlsi_dir) && cp output.json $@
#########################################################################################
# simulation input configuration
#########################################################################################
include $(base_dir)/vcs.mk
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
include $(vlsi_dir)/sim.mk
$(SIM_CONF): $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $(shell cat $(sim_common_files)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@
for x in $(filter-out -f $(sim_common_files),$(VCS_NONCC_OPTS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " options_meta: 'append'" >> $@
echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " defines_meta: 'append'" >> $@
echo " compiler_cc_opts:" >> $@
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_cc_opts_meta: 'append'" >> $@
echo " compiler_ld_opts:" >> $@
for x in $(filter-out "",$(VCS_LDFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_ld_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags:" >> $@
for x in $(SIM_FLAGS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@
endif
echo " tb_dut: 'TestDriver.testHarness.$(VLSI_MODEL_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(sim_common_files)
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
else
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
endif
$(SIM_TIMING_CONF): $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@
POWER_CONF = $(OBJ_DIR)/power-inputs.yml
include $(vlsi_dir)/power.mk
$(POWER_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "power.inputs:" > $@
echo " tb_dut: 'testHarness/$(VLSI_MODEL_DUT_NAME)'" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
ifneq ($(BINARY), )
echo " waveforms: [" >> $@
ifndef USE_VPD
echo " '$(sim_out_name).fsdb'" >> $@
else
echo " '$(sim_out_name).vpd'" >> $@
endif
echo " ]" >> $@
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
#########################################################################################
# synthesis input configuration
#########################################################################################
@@ -243,6 +127,27 @@ $(SYN_CONF): $(VLSI_RTL)
echo ' - "'$$x'"' >> $@; \
done
#########################################################################################
# simulation and power input configuration
#########################################################################################
include $(base_dir)/vcs.mk
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
include $(vlsi_dir)/sim.mk
include $(vlsi_dir)/power.mk
#########################################################################################
# AUTO BUILD FLOW
#########################################################################################