wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Explicitly pass chipId to all HarnessBinders

Browse Source
This commit is contained in:
Jerry Zhao
2023-12-26 18:37:39 -08:00
parent 3885e79f77
commit 835562238a
11 changed files with 64 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/src/main/scala/vcu118/HarnessBinders.scala
View File

@@ -15,21 +15,21 @@ import chipyard.iobinders._
/*** UART ***/
class WithUART extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: UARTPort) => {
case (th: VCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
th.vcu118Outer.io_uart_bb.bundle <> port.io
}
})
/*** SPI ***/
class WithSPISDCard extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: SPIPort) => {
case (th: VCU118FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
th.vcu118Outer.io_spi_bb.bundle <> port.io
}
})
/*** Experimental DDR ***/
class WithDDRMem extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: TLMemPort) => {
case (th: VCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
val bundles = th.vcu118Outer.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }

10
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
View File

@@ -18,34 +18,34 @@ import chipyard.iobinders._
/*** UART ***/
class WithBringupUART extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
}
})
/*** I2C ***/
class WithBringupI2C extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort, chipId: Int) => {
th.bringupOuter.io_i2c_bb.bundle <> port.io
}
})
/*** GPIO ***/
class WithBringupGPIO extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort, chipId: Int) => {
th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
}
})
/*** TSI Host Widget ***/
class WithBringupTSIHost extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
tsiDdrClientBundle <> port.io
}
case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort, chipId: Int) => {
th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
}
})