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Explicitly pass chipId to all HarnessBinders

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This commit is contained in:
Jerry Zhao
2023-12-26 18:37:39 -08:00
parent 3885e79f77
commit 835562238a
11 changed files with 64 additions and 64 deletions
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6
fpga/src/main/scala/vc707/HarnessBinders.scala
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@@ -16,21 +16,21 @@ import chipyard.iobinders._
/*** UART ***/
class WithVC707UARTHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: UARTPort) => {
case (th: VC707FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
th.vc707Outer.io_uart_bb.bundle <> port.io
}
})
/*** SPI ***/
class WithVC707SPISDCardHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: SPIPort) => {
case (th: VC707FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
th.vc707Outer.io_spi_bb.bundle <> port.io
}
})
/*** Experimental DDR ***/
class WithVC707DDRMemHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: TLMemPort) => {
case (th: VC707FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
val bundles = th.vc707Outer.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }