wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Explicitly pass chipId to all HarnessBinders

Browse Source
This commit is contained in:
Jerry Zhao
2023-12-26 18:37:39 -08:00
parent 3885e79f77
commit 835562238a
11 changed files with 64 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/src/main/scala/nexysvideo/HarnessBinders.scala
View File

@@ -15,7 +15,7 @@ import chipyard.harness._
import chipyard.iobinders._
class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
nexysvideoth.io_uart_bb.bundle <> port.io.uart
nexysvideoth.other_leds(1) := port.io.dropped
@@ -27,7 +27,7 @@ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder
})
class WithNexysVideoDDRTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: TLMemPort) => {
case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
val bundles = nexysTh.ddrClient.get.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))