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Explicitly pass chipId to all HarnessBinders

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This commit is contained in:
Jerry Zhao
2023-12-26 18:37:39 -08:00
parent 3885e79f77
commit 835562238a
11 changed files with 64 additions and 64 deletions
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8
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
import chipyard.iobinders._
class WithArtyDebugResetHarnessBinder extends HarnessBinder({
case (th: Arty35THarness, port: DebugResetPort) => {
case (th: Arty35THarness, port: DebugResetPort, chipId: Int) => {
th.dut_ndreset := port.io // Debug module reset
}
})
class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
case (th: Arty35THarness, port: JTAGResetPort) => {
case (th: Arty35THarness, port: JTAGResetPort, chipId: Int) => {
port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
}
})
class WithArtyJTAGHarnessBinder extends HarnessBinder({
case (th: Arty35THarness, port: JTAGPort) => {
case (th: Arty35THarness, port: JTAGPort, chipId: Int) => {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := port.io.TDO
jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
})
class WithArtyUARTHarnessBinder extends HarnessBinder({
case (th: Arty35THarness, port: UARTPort) => {
case (th: Arty35THarness, port: UARTPort, chipId: Int) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_rxd_out, port.io.txd)
port.io.rxd := IOBUF(th.uart_txd_in)

6
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -22,7 +22,7 @@ import chipyard.iobinders._
import testchipip.serdes._
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
ath.io_uart_bb.bundle <> port.io.uart
ath.other_leds(1) := port.io.dropped
@@ -34,7 +34,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
})
class WithArty100TDDRTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: TLMemPort) => {
case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val bundles = artyTh.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
@@ -45,7 +45,7 @@ class WithArty100TDDRTL extends HarnessBinder({
// Uses PMOD JA/JB
class WithArty100TSerialTLToGPIO extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort) => {
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
harnessIO <> port.io

4
fpga/src/main/scala/nexysvideo/HarnessBinders.scala
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@@ -15,7 +15,7 @@ import chipyard.harness._
import chipyard.iobinders._
class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
nexysvideoth.io_uart_bb.bundle <> port.io.uart
nexysvideoth.other_leds(1) := port.io.dropped
@@ -27,7 +27,7 @@ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder
})
class WithNexysVideoDDRTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: TLMemPort) => {
case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
val bundles = nexysTh.ddrClient.get.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))

6
fpga/src/main/scala/vc707/HarnessBinders.scala
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@@ -16,21 +16,21 @@ import chipyard.iobinders._
/*** UART ***/
class WithVC707UARTHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: UARTPort) => {
case (th: VC707FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
th.vc707Outer.io_uart_bb.bundle <> port.io
}
})
/*** SPI ***/
class WithVC707SPISDCardHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: SPIPort) => {
case (th: VC707FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
th.vc707Outer.io_spi_bb.bundle <> port.io
}
})
/*** Experimental DDR ***/
class WithVC707DDRMemHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: TLMemPort) => {
case (th: VC707FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
val bundles = th.vc707Outer.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }

6
fpga/src/main/scala/vcu118/HarnessBinders.scala
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@@ -15,21 +15,21 @@ import chipyard.iobinders._
/*** UART ***/
class WithUART extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: UARTPort) => {
case (th: VCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
th.vcu118Outer.io_uart_bb.bundle <> port.io
}
})
/*** SPI ***/
class WithSPISDCard extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: SPIPort) => {
case (th: VCU118FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
th.vcu118Outer.io_spi_bb.bundle <> port.io
}
})
/*** Experimental DDR ***/
class WithDDRMem extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: TLMemPort) => {
case (th: VCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
val bundles = th.vcu118Outer.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }

10
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
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@@ -18,34 +18,34 @@ import chipyard.iobinders._
/*** UART ***/
class WithBringupUART extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
}
})
/*** I2C ***/
class WithBringupI2C extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort, chipId: Int) => {
th.bringupOuter.io_i2c_bb.bundle <> port.io
}
})
/*** GPIO ***/
class WithBringupGPIO extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort, chipId: Int) => {
th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
}
})
/*** TSI Host Widget ***/
class WithBringupTSIHost extends HarnessBinder({
case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
tsiDdrClientBundle <> port.io
}
case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort) => {
case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort, chipId: Int) => {
th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
}
})