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Upstream MemConf and use it (with some slight tweaks)

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John Wright
2019-03-05 15:01:44 -08:00
committed by Colin Schmidt
parent c23b2b6f84
commit 82636b3ff4
3 changed files with 4 additions and 61 deletions
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4
macros/src/main/scala/Utils.scala
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@@ -5,6 +5,7 @@ package barstools.macros
import firrtl._
import firrtl.ir._
import firrtl.PrimOps
import firrtl.passes.memlib.{MemConf, MemPort, ReadPort, WritePort, ReadWritePort, MaskedWritePort, MaskedReadWritePort}
import firrtl.Utils.{ceilLog2, BoolType}
import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge, MacroExtraPort}
@@ -78,7 +79,8 @@ object Utils {
}
def readConfFromString(str: String): Seq[mdf.macrolib.Macro] = {
MemConf.fromString(str).map { m:MemConf =>
SRAMMacro(m.name, m.width, m.depth, Utils.portSpecToFamily(m.ports), Utils.portSpecToMacroPort(m.width, m.depth, m.maskGranularity, m.ports))
val ports = m.ports.map { case (port, num) => Seq.fill(num)(port) } reduce (_ ++ _)
SRAMMacro(m.name, m.width, m.depth, Utils.portSpecToFamily(ports), Utils.portSpecToMacroPort(m.width, m.depth, m.maskGranularity, ports))
}
}
def portSpecToFamily(ports: Seq[MemPort]): String = {