diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
new file mode 100644
index 00000000..3b802c57
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -0,0 +1,38 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.subsystem.{SBUS}
+import testchipip.soc.{OBUS}
+
+// ------------------------------------------------
+// Configs demonstrating chip-to-chip communication
+// ------------------------------------------------
+
+// Simple design which exposes a second serial-tl port that can connect to another instance of itself
+class SymmetricChipletRocketConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(                               // 0th serial-tl is chip-to-bringup-fpga
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // bringup serial-tl acts only as a client
+      phyParams = testchipip.serdes.ExternalSyncSerialParams()      // bringup serial-tl is sync'd to external clock
+    ),
+    testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // chip-to-chip serial-tl acts as a client
+      manager = Some(testchipip.serdes.SerialTLManagerParams(       // chip-to-chip serial-tl managers other chip's memory
+        memParams = Seq(testchipip.serdes.ManagerRAMParams(
+          address = 0,
+          size = 1L << 32,
+        )),
+        slaveWhere = OBUS
+      )),
+      phyParams = testchipip.serdes.SourceSyncSerialParams()        // chip-to-chip serial-tl is symmetric source-sync'd
+    ))
+  ) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS,                     // obus provides path to other chip's memory
+    blockRange = Seq(AddressSet(0, (1L << 32) - 1)),                // The lower 4GB is mapped to this chip
+    replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
+  ) ++
+  new testchipip.soc.WithOffchipBus ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index a29cf5c0..a50f1743 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -205,23 +205,32 @@ class WithTiedOffDMI extends HarnessBinder({
   }
 })
 
-class WithSerialTLTiedOff extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+// If tieoffs is specified, a list of serial portIds to tie off
+// If tieoffs is unspecified, ties off all serial ports
+class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: SerialTLPort) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
     port.io match {
       case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
+      case io: SourceSyncSerialIO => {
+        io.clock_in := false.B.asClock
+        io.reset_in := false.B.asAsyncReset
+        io.in := DontCare
+        io.credit_in := DontCare
+      }
     }
     port.io match {
       case io: InternalSyncSerialIO =>
       case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
+      case _ =>
     }
   }
 })
 
 class WithSimTSIOverSerialTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+  case (th: HasHarnessInstantiators, port: SerialTLPort) if (port.portId == 0) => {
     port.io match {
       case io: InternalSyncSerialIO =>
-      case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
+      case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
     }
 
     port.io match {
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index e159e345..9cd6afd2 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -65,9 +65,20 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
       clkSink.in <> clkSource.out
       clkSource.in <> clkSink.out
     }
+    def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
+      a.clock_in := b.clock_out
+      b.clock_in := a.clock_out
+      a.reset_in := b.reset_out
+      b.reset_in := a.reset_out
+      a.in := b.out
+      b.in := a.out
+      a.credit_in := b.credit_out
+      b.credit_in := a.credit_out
+    }
     (p0.io, p1.io) match {
       case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
       case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
+      case (io0: SourceSyncSerialIO  , io1: SourceSyncSerialIO  ) => connectSourceSyncSerialIO   (io0, io1)
     }
   }
 )
diff --git a/generators/testchipip b/generators/testchipip
index 9011ac85..11551255 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 9011ac8530f8186e013409f0e2d65f54b2b512d4
+Subproject commit 11551255834ff4f98c1474a806b7c733cb53d6ee