Add arty100t harness binder to map UART to PMOD JD
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@@ -25,7 +25,17 @@ import testchipip._
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class WithArty100TUARTTSI extends HarnessBinder({
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case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
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val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
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ath.io_uart_bb.bundle <> port.io.uart
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val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi")
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harnessIO <> port.io
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val packagePinsWithPackageIOs = Seq(
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("A9" , IOPin(harnessIO.uart.rxd)),
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("D10", IOPin(harnessIO.uart.txd)))
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packagePinsWithPackageIOs foreach { case (pin, io) => {
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ath.xdc.addPackagePin(io, pin)
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ath.xdc.addIOStandard(io, "LVCMOS33")
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ath.xdc.addIOB(io)
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} }
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ath.other_leds(1) := port.io.dropped
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ath.other_leds(9) := port.io.tsi2tl_state(0)
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ath.other_leds(10) := port.io.tsi2tl_state(1)
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@@ -34,6 +44,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
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}
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})
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class WithArty100TDDRTL extends HarnessBinder({
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case (th: HasHarnessInstantiators, port: TLMemPort) => {
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val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
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@@ -83,3 +94,23 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
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artyTh.xdc.clockDedicatedRouteFalse(clkIO)
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}
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})
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// Maps the UART device to the on-board USB-UART
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class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
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case (th: HasHarnessInstantiators, port: UARTPort) => {
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val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
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val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
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harnessIO <> port.io
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val packagePinsWithPackageIOs = Seq(
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(rxdPin, IOPin(harnessIO.rxd)),
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(txdPin, IOPin(harnessIO.txd)))
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packagePinsWithPackageIOs foreach { case (pin, io) => {
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ath.xdc.addPackagePin(io, pin)
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ath.xdc.addIOStandard(io, "LVCMOS33")
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ath.xdc.addIOB(io)
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} }
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}
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})
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// Maps the UART device to PMOD JD pins 3/7
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class WithArty100TPMODUART extends WithArty100TUART("E2", "F4")
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